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164
Revision 1.1
G
Core Logic Module
(Continued)
Table 5-28. ISA Legacy I/O Register Summary
I/O Port
Type
Name
Reference
DMA Channel Control Registers (Table 5-43)
000h
001h
002h
003h
004h
005h
006h
007h
008h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read
Write
WO
W
WO
WO
WO
WO
WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read
Write
WO
W
WO
WO
WO
WO
WO
DMA Channel 0 Address Register
DMA Channel 0 Transfer Count Register
DMA Channel 1 Address Register
DMA Channel 1 Transfer Count Register
DMA Channel 2 Address Register
DMA Channel 2 Transfer Count Register
DMA Channel 3 Address Register
DMA Channel 3 Transfer Count Register
DMA Status Register, Channels 3:0
DMA Command Register, Channels 3:0
Software DMA Request Register, Channels 3:0
DMA Channel Mask Register, Channels 3:0
DMA Channel Mode Register, Channels 3:0
DMA Clear Byte Pointer Command, Channels 3:0
DMA Master Clear Command, Channels 3:0
DMA Clear Mask Register Command, Channels 3:0
DMA Write Mask Register Command, Channels 3:0
DMA Channel 4 Address Register (Not used)
DMA Channel 4 Transfer Count Register (Not Used)
DMA Channel 5 Address Register
DMA Channel 5 Transfer Count Register
DMA Channel 6 Address Register
DMA Channel 6 Transfer Count Register
DMA Channel 7 Address Register
DMA Channel 7 Transfer Count Register
DMA Status Register, Channels 7:4
DMA Command Register, Channels 7:4
Software DMA Request Register, Channels 7:4
DMA Channel Mask Register, Channels 7:4
DMA Channel Mode Register, Channels 7:4
DMA Clear Byte Pointer Command, Channels 7:4
DMA Master Clear Command, Channels 7:4
DMA Clear Mask Register Command, Channels 7:4
DMA Write Mask Register Command, Channels 7:4
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009h
00Ah
00Bh
00Ch
00Dh
00Eh
00Fh
0C0h
0C2h
0C4h
0C6h
0C8h
0CAh
0CCh
0CEh
0D0h
0D2h
0D4h
0D6h
0D8h
0DAh
0DCh
0DEh
DMA Page Registers (Table 5-44)
081h
082h
083h
087h
089h
08Ah
08Bh
08Fh
481h
482h
483h
487h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA Channel 2 Low Page Register
DMA Channel 3 Low Page Register
DMA Channel 1 Low Page Register
DMA Channel 0 Low Page Register
DMA Channel 6 Low Page Register
DMA Channel 7 Low Page Register
DMA Channel 5 Low Page Register
Sub-ISA Refresh Low Page Register
DMA Channel 2 High Page Register
DMA Channel 3 High Page Register
DMA Channel 1 High Page Register
DMA Channel 0 High Page Register
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