www.national.com
126
Revision 1.1
G
Core Logic Module
(Continued)
5.2.5.6
The Core Logic module positively decodes memory
addresses
000F0000h-000FFFFFh
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
ROM Interface
(64
KB)
and
8- or 16-bit wide ROM is supported. BOOT16 strap deter-
mines the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block (see Table 3-2 on page 50 for
bit details) allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#, WR# and ROMCS#
asserted.
5.2.5.7
The SC1100 multiplexes most PCI and Sub-ISA signals on
the balls listed in Table 5-3, in order to reduce the number
of balls on the device. Cycle multiplexing is on a bus-cycle
by bus-cycle basis (see Figure 5-6 on page 127), where the
internal Core Logic PCI bridge arbitrates between PCI
cycles and Sub-ISA cycles. Other PCI and Sub-ISA signals
remain non-shared, however, some Sub-ISA signals may
be muxed with GPIO.
PCI and Sub-ISA Signal Cycle Multiplexing
Sub-ISA cycles are only generated as a result of GX1 mod-
ule accesses to the following addresses or conditions:
ROMCS# address range.
DOCCS# address range.
F5BAR4CS address range.
F5BAR5CS address range.
IOCS0# address range.
IOCS1# address range.
An I/O write to address 80h or to 84h.
If the Sub-ISA and PCI bus have more than four compo-
nents, the Sub-ISA components can be buffered using
74HCT245 or 74FCT245 type transceivers. The RD# (an
AND of IOR#, MEMR#) signal can be used as DIR control
while TRDE# is used as enable control.
Table 5-3. Cycle Multiplexed PCI / Sub-ISA Balls
PCI
Sub-ISA
Ball No.
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PAR
TRDY#
IRDY#
STOP#
DEVSEL#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
BHE#
E25
F26
F25
G26
G25
H26
H25
D24
E23
J26
J25
K25
K26
F23
F24
L26
R25
K24
T26
T25
L24
U26
U25
M24
V25
W26
N24
P24
W25
Y26
R24
Y25
E24
G24
R26
V26
H24
N25
P26
M25
N26