參數(shù)資料
型號: TE28F800C3TD70
廠商: INTEL CORP
元件分類: PROM
英文描述: 512K X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝: 12 X 20 MM, TSOP-48
文件頁數(shù): 18/72頁
文件大小: 1083K
代理商: TE28F800C3TD70
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Order Number: 290645, Revision: 023
25
7.0
AC Characteristics
7.1
AC Read Characteristics
Table 8.
Read Operations—8-Mbit Density
#Sym
Parameter
Density
8 Mbit
Product
70 ns
90 ns
110 ns
VCC
2.7 V – 3.6 V
3.0 V – 3.6 V
2.7 V – 3.6 V
3.0 V – 3.6 V
2.7 V – 3.6 V
Note
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
R1
tAVAV
Read Cycle Time
3,4
70
80
90
100
110
R2
tAVQV
Address to
Output Delay
3,4
70
80
90
100
110
R3
tELQV
CE# to Output
Delay
1,3,4
70
80
90
100
110
R4
tGLQV
OE# to Output
Delay
1,3,4
20
30
R5
tPHQV
RP# to Output
Delay
3,4
150
R6
tELQX
CE# to Output in
Low Z
2,3,4
0
R7
tGLQX
OE# to Output in
Low Z
2,3,4
0
R8
tEHQZ
CE# to Output in
High Z
2,3,4
20
R9
tGHQZ
OE# to Output in
High Z
2,3,4
20
R10
tOH
Output Hold from
Address, CE#, or
OE# Change,
Whichever
Occurs First
2,3,4
0
Notes:
1.OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2.Sampled, but not 100% tested.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timing measurements and maximum allowable input
slew rate.
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