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參數(shù)資料
| 型號： | TE28F800C3TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 512K X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 26/72頁 |
| 文件大?。?/td> | 1083K |
| 代理商： | TE28F800C3TD70 |
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Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
32
Order Number: 290645, Revision: 023
Table 15.
Write Operations—64-Mbit Density
#
Symbol
Parameter
Density
64 Mbit
Unit
Product
80 ns
VCC
2.7 V – 3.6 V
Note
Min
W1
tPHWL / tPHEL
RP# High Recovery to WE# (CE#) Going Low
4,5
150
ns
W2
tELWL / tWLEL
CE# (WE#) Setup to WE# (CE#) Going Low
4,5
0
ns
W3
tWLWH / tELEH
WE# (CE#) Pulse Width
1,4,5
60
ns
W4
tDVWH / tDVEH
Data Setup to WE# (CE#) Going High
2,4,5
40
ns
W5
tAVWH / tAVEH
Address Setup to WE# (CE#) Going High
2,4,5
60
ns
W6
tWHEH / tEHWH
CE# (WE#) Hold Time from WE# (CE#) High
4,5
0
ns
W7
tWHDX / tEHDX
Data Hold Time from WE# (CE#) High
2,4,5
0
ns
W8
tWHAX / tEHAX
Address Hold Time from WE# (CE#) High
2,4,5
0
ns
W9
tWHWL / tEHEL
WE# (CE#) Pulse Width High
1,4,5
30
ns
W10
tVPWH / tVPEH
VPP Setup to WE# (CE#) Going High
3,4,5
200
ns
W11
tQVVL
VPP Hold from Valid SRD
3,4
0
ns
W12
tBHWH / tBHEH
WP# Setup to WE# (CE#) Going High
3,4
0
ns
W13
tQVBL
WP# Hold from Valid SRD
3,4
0
ns
W14
tWHGL
WE# High to OE# Going Low
3,4
30
ns
Notes:
1.Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever
goes high first). Hence, tWP =tWLWH =tELEH =tWLEH =tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or
WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
tWPH =tWHWL =tEHEL =tWHEL =tEHWL.
3.Sampled, but not 100% tested.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timing measurements and maximum allowable input
slew rate.
Figure 10.
Write Operations Waveform
W10
W1
W7
W4
W9
W3
W2
W6
W8
W5
Address [A]
CE# [E]
WE# [W]
OE# [G]
Data [D/Q]
RP# [P]
Vpp [V]
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