參數(shù)資料
型號(hào)： TE28F800C3TD70
廠商： INTEL CORP
元件分類： PROM
英文描述： 512K X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝： 12 X 20 MM, TSOP-48
文件頁(yè)數(shù)： 43/72頁(yè)
文件大?。?/td> 1083K
代理商： TE28F800C3TD70
Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
48
Order Number: 290645, Revision: 023
Table 24.
Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7654
3210
NOTES:
SR[7] WRITE STATE MACHINE STATUS (WSMS)
1= Ready
0= Busy
Before checking program or erase- status bits, check the Write
State Machine bit first to determine Word Program or Block
Erase completion.
SR[6] = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until
an Erase Resume command is issued.
SR[5] = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the maximum
number of erase pulses to the block and is still unable to verify
successful block erasure.
SR[4] = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
SR[3] = VPP STATUS (VPPS)
1= VPP Low Detect, Operation Abort
0= VPP OK
The VPP status bit does not provide continuous indication of
VPP level. The WSM interrogates VPP level only after the
Program or Erase command sequences have been entered
and informs the system if VPP has not been switched on. The
VPP is also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report accurate
feedback between VPPLK and VPP1Min.
SR[2] = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
SR[1] = BLOCK LOCK STATUS
1 = Prog/Erase attempted on a locked block; Operation
aborted.
0 = No operation to locked blocks
If a Program or Erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read status
mode.
SR[0] = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out
when polling the Status Register.
Note:
A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set.
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