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參數(shù)資料
| 型號： | TE28F800C3TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 512K X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 47/72頁 |
| 文件大?。?/td> | 1083K |
| 代理商： | TE28F800C3TD70 |
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Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Order Number: 290645, Revision: 023
51
11.3
Locking Operations during Erase Suspend
Changes to block-lock status can be performed during an erase-suspend by using the standard
locking command sequences to Unlock, Lock, or Lock Down a block. This operation is useful in
the case when another block needs to be updated while an Erase operation is in progress.
To change block locking during an Erase operation, first issue the Erase Suspend command (0xB0),
and then check the Status Register until it indicates that the Erase operation has been suspended.
Next, write the preferred Lock command sequence to a block and the Lock status will be changed.
After completing any preferred Lock, Read, or Program operations, resume the Erase operation
with the Erase Resume command (0xD0).
If a block is Locked or Locked Down during a Suspended Erase of the same block, the locking
status bits will be changed immediately. But when the Erase is resumed, the Erase operation will
complete.
Locking operations cannot be performed during a Program Suspend. Refer to Appendix A, “Write
State Machine States” on page 54 for detailed information on which commands are valid during
Erase Suspend.
11.4
Status Register Error Checking
Using nested-locking or program-command sequences during Erase Suspend can introduce
ambiguity into Status Register results.
Since locking changes are performed using a two-cycle command sequence, for example, 0x60
followed by 0x01 to lock a block. Following the Block Lock, Block Unlock, or Block Lock-Down
Setup command (0x60) with an invalid command will produce a Lock-Command error (SR[4] and
SR[5] will be set to 1) in the Status Register. If a Lock-Command error occurs during an Erase
Suspend, SR[4] and SR[5] will be set to 1 and will remain at 1 after the Erase is resumed. When
Erase is complete, any possible error during the Erase cannot be detected by the Status Register
because of the previous Lock-Command error.
A similar situation happens if an error occurs during a Program-Operation error nested within an
Erase Suspend.
11.5
128-Bit Protection Register
The C3 device architecture includes a 128-bit protection register than can be used to increase the
security of a system design. For example, the number contained in the protection register can be
used to “match” the flash component with other system components, such as the CPU or ASIC,
preventing device substitution. Application note, AP-657 Designing with the Advanced+ Boot
Block Flash Memory Architecture,
contains additional application information.
The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other
segment is left blank for customer designs to program, as preferred. Once the customer segment is
programmed, it can be locked to prevent further programming.
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