參數(shù)資料
型號： TE28F800C3TD70
廠商： INTEL CORP
元件分類： PROM
英文描述： 512K X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝： 12 X 20 MM, TSOP-48
文件頁數(shù)： 48/72頁
文件大?。?/td> 1083K
代理商： TE28F800C3TD70
Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
52
Order Number: 290645, Revision: 023
11.5.1
Reading the Protection Register
The protection register is read in the Read-Identifier mode. The device is switched to this mode by
issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown
in Figure 15, “Protection Register Mapping” retrieve the specified information. To return to Read-
Array mode, issue the Read Array command (0xFF).
11.5.2
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time. First, issue the Protection Program Setup
command, 0xC0. The next write to the device will latch in address and data and program the
specified location. The allowable addresses are listed in Table 21, “Device Identification Codes”
to program to a previously locked protection register segment will result in a Status Register error
(Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1).
Note:
Do not attempt to address Protection Program commands outside the defined protection register
address space; status register can be indeterminate.
11.5.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming bit 1 of the
PR-LOCK location to 0. See Figure 15, “Protection Register Mapping” on page 52. Bit 0 of this
location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set
using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these
bits have been programmed, no further changes can be made to the values stored in the protection
register. Protection Program commands to a locked section will result in a Status Register error
(Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1). Protection register lockout
state is not reversible.
11.6
VPP Program and Erase Voltages
The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range. For fast
production programming, 12 V programming can be used. See Figure 16, “Example Power Supply
Figure 15.
Protection Register Mapping
0x88
0x85
64-bit Segment
(User-Programmable)
0x84
0x81
0x80
PR Lock Register 0
64-bit Segment
(Intel Factory-Programmed)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
128-Bit Protection Register 0
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