參數(shù)資料
型號: TE28F800C3TD70
廠商: INTEL CORP
元件分類: PROM
英文描述: 512K X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝: 12 X 20 MM, TSOP-48
文件頁數(shù): 22/72頁
文件大?。?/td> 1083K
代理商: TE28F800C3TD70
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Order Number: 290645, Revision: 023
29
7.2
AC Write Characteristics
Table 12.
Write Operations—8-Mbit Density
#Sym
Parameter
Density
8 Mbit
Product
70ns
90 ns
110 ns
VCC
3.0 V – 3.6 V
80
100
2.7 V – 3.6 V
70
90
110
Note
Min
(ns)
Min
(ns)
Min
(ns)
Min
(ns)
Min
(ns)
W1
tPHWL /
tPHEL
RP# High Recovery to WE# (CE#) Going Low
4,5
150
W2
tELWL /
tWLEL
CE# (WE#) Setup to WE# (CE#) Going Low
4,5
0000
0
W3
tWLWH /
tELEH
WE# (CE#) Pulse Width
4,5
45
50
60
70
W4
tDVWH /
tDVEH
Data Setup to WE# (CE#) Going High
2,4,5
40
50
60
W5
tAVWH /
tAVEH
Address Setup to WE# (CE#) Going High
2,4,5
50
60
70
W6
tWHEH /
tEHWH
CE# (WE#) Hold Time from WE# (CE#) High
4,5
0000
0
W7
tWHDX /
tEHDX
Data Hold Time from WE# (CE#) High
2,4,5
0000
0
W8
tWHAX /
tEHAX
Address Hold Time from WE# (CE#) High
2,4,5
0000
0
W9
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
2,4,5
25
30
W10
tVPWH /
tVPEH
VPP Setup to WE# (CE#) Going High
3,4,5
200
W11
tQVVL
VPP Hold from Valid SRD
3,4
0000
0
W12
tBHWH /
tBHEH
WP# Setup to WE# (CE#) Going High
3,4
0000
0
W13
tQVBL
WP# Hold from Valid SRD
3,4
0000
0
W14
tWHGL
WE# High to OE# Going Low
3,4
30
Notes:
1.Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever
goes high first). Hence, tWP =tWLWH =tELEH =tWLEH =tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or
WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
tWPH =tWHWL =tEHEL =tWHEL =tEHWL.
3.Sampled, but not 100% tested.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timing measurements and maximum allowable input
slew rate.
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