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參數(shù)資料
| 型號(hào)： | TE28F800C3TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 512K X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 31/72頁 |
| 文件大?。?/td> | 1083K |
| 代理商： | TE28F800C3TD70 |
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Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Order Number: 290645, Revision: 023
37
8.5.4
Reset Specifications
8.6
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System
designers should consider the following three supply current issues:
Standby current levels (ICCS)
Read current levels (ICCR)
Transient peaks produced by falling and rising edges of CE#.
Table 19.
Reset Specifications
Symbol
Parameter
VCC 2.7 V – 3.6 V
Unit
Notes
Min
Max
tPLPH
RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not
applicable)
100
ns
1, 2
tPLRH1
RP# Low to Reset during Block Erase
22
s
3
tPLRH2
RP# Low to Reset during Program
12
s
3
Notes:
1.If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
2.If RP# is asserted while a Block Erase or Word Program operation is not executing, the reset
will complete within 100 ns.
3.Sampled, but not 100% tested.
Figure 13.
Reset Operations Waveforms
IH
V
IL
V
RP# (P)
PLPH
t
IH
V
IL
V
RP# (P)
PLPH
t
(A) Reset during Read Mode
Abort
Complete
PHQV
t
PHWL
t
PHEL
t
PHQV
t
PHWL
t
PHEL
t
(B) Reset during Program or Block Erase,
<
PLPH
t
PLRH
t
PLRH
t
IH
V
IL
V
RP# (P)
PLPH
t
Abort
Complete
PHQV
t
PHWL
t
PHEL
t
PLRH
t
Deep
Power-
Down
(C) Reset Program or Block Erase,
>
PLPH
t
PLRH
t
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