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參數(shù)資料
| 型號(hào)： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 19/90頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
5
Lucent Technologies Inc.
Description
(continued)
On the STS-1 side, the device can be configured for either a serial bit stream or an 8-bit parallel bus. This allows
the device to drive an OC-1 optical signal directly and also allows for modular growth in terminal or add/drop appli-
cations.
On the DS1/E1 side, the device is designed to interface with the Lucent T7698FL3/T7693 Quad Line Transceiver,
or equivalent, using the internal digital jitter attenuator buffer for PLL-free operation.
The TMPR28051 device contains built-in test pattern insertion and drop that allows end-to-end testing for initial
setup or maintenance without the need for external test equipment. Built-in loopbacks at both the STS-1 and DS1/
E1 sides provide maximum flexibility for use in a number of SONET/SDH or DS1/E1 products including terminal
multiplexers, add/drop multiplexers, and digital cross connects. A high-speed microprocessor interface and full
user programmability for VT slot insertion and drop provide maximum flexibility for DS1/E1 I/O configuration.
Block Diagram
The block diagram is shown in Figure 1. For illustration purposes, only two of the DS1/E1 bidirectional blocks are
shown.
5-4875(F).ar.10
Note: “n” represents 28 or 21 for DS1 or E1, respectively.
Figure 1. Block Diagram
MICROPROCESSOR
INTERFACE
STS-1/AU-3
TERMINATE
DS1/E1 #1 IN
ELASTIC
STORE
SPE
INSERTION
LOGIC
VT
GENERATE
ELASTIC
STORE
VT
GENERATE
DS1/E1 #n IN
STS-1/AU-3
GENERATE
DS1/E1 #1 OUT
SPE
DROP
LOGIC
VT
TERMINATE
VT
TERMINATE
DS1/E1 #n OUT
STS-1/AU-3 IN
INPUT
SELECT
LOGIC
LOOP-
BACK
SELECT
LOGIC
INPUT
SELECT
LOGIC
SPE
LOCATE
DROP
SELECT
LOGIC
LOC AND
AIS
MONITOR
TEST
PATTERN
INSERT
TEST
PATTERN
DROP
LOOP-
BACK
SELECT
LOGIC
DROP
SELECT
LOGIC
LOOP-
BACK
SELECT
LOGIC
STS-1/AU-3 OUT
LOC AND
AIS
MONITOR
JITTER
ATTENUATE
JITTER
ATTENUATE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMPR28051-3-SL5 | 制造商:AGERE 制造商全稱:AGERE 功能描述:TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| TMPR28051-SL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET MAPPER|QFP|208PIN|PLASTIC |
| TMPR3904F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|208PIN|PLASTIC |
| TMPR3907F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|208PIN|PLASTIC |
| TMPR3911 | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:32-Bit TX System RISC TX39 Family |
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