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    參數(shù)資料
    型號(hào): TMPR28051
    英文描述: TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
    中文描述: TMPR28051 STS-1/AU-3(的STM - 0)映射為版本的設(shè)備5設(shè)備咨詢
    文件頁數(shù): 68/90頁
    文件大?。?/td> 1090K
    代理商: TMPR28051
    Data Sheet
    August 1999
    TMPR28051 STS-1/AU-3 (STM-0) Mapper
    54
    Lucent Technologies Inc.
    Microprocessor Interface Description
    (continued)
    Register Architecture Description
    (continued)
    Digital Jitter Attenuator Controls (0x8A—0x8F)
    Table 24. Registers 0x8A—0x8F: Digital Jitter Attenuator Controls
    Address
    (Hex)
    Bit #
    Name
    Function
    Reset
    Default
    (Hex)
    See
    below.
    0x8A—0x8F
    The bits in registers 0x8A—0x8F are used to control vari-
    ous aspects of the digital jitter attenuator. Two programma-
    ble terms are used to set the 2nd order loop damping factor
    and natural frequency of the PLL. These terms are the gain
    threshold, set by DJAGTHR-[23:0] in registers
    0x8D—0x8F, and scale value, set by DJASCALE-[15:0] in
    registers 0x8B—0x8C. The PLL bandwidth can be set,
    using the above registers, to accommodate various system
    constraints.
    SCALETHR-[7:0] Scale Threshold.
    DJASCALE-[15:8] Scale Value.
    DJASCALE-[7:0]
    DJAGTHR-[23:16]
    Gain Threshold.
    DJAGTHR-[15:8]
    DJAGTHR-[7:0]
    0x8A
    0x8B
    0x8C
    0x8D
    0x8E
    0x8F
    7—0
    7—0
    7—0
    7—0
    7—0
    7—0
    0xFF
    0x0F
    0xCA
    0x00
    0xFE
    0x50
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