參數(shù)資料
型號: TMPR28051
英文描述: TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述: TMPR28051 STS-1/AU-3(的STM - 0)映射為版本的設(shè)備5設(shè)備咨詢
文件頁數(shù): 59/90頁
文件大?。?/td> 1090K
代理商: TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
45
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Table 15
.
Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits
(continued)
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0x11
The bits in register 0x11 are used to set the values to be
transmitted in the G1 and K2 bytes.
The G1INS-[5:8] bits are used to set values to be transmit-
ted in the four least significant bits of the G1 byte. The
G1 byte is written by the microprocessor.
7
6
5
4
3
2
1
0
G1INS-5
G1INS-6
G1INS-7
G1INS-8
K2INS-6
K2INS-7
K2INS-8
Reserved.
The K2INS-[6:8] bits are used to set the values to be trans-
mitted in the three least significant bits of the K2 byte.
AUTO_LRDI bit (bit 6 of register 0x01) should be set to 0
for K2INS-[6:8] insertion (i.e., K2 insertion) through the
microprocessor interface.
The bits in register 0x12 are used to set the bus mode of
operation for both the transmit and receive sides.
Reserved.
The RBUSMODE bit sets the STS-1 receive side of the
device to the bus mode of operation when a 1; otherwise,
the device is set to nonbus mode.
The RBUSPOS-[1:0] sets the time slot for the receive side.
00 causes the receive side not to listen. Otherwise, the
time slots are determined by the binary value of these bits
as follows:
01 = time slot 1
10 = time slot 2
11 = time slot 3
The TBUSMODE bit sets the STS-1 transmit side of the
device to the bus mode of operation when a 1; otherwise,
the device is set to nonbus mode.
The TBUSPOS-[1:0] sets the time slot for the transmit
sides. 00 causes the transmit side not to transmit. Other-
wise, the time slots are determined by the binary value of
these bits as follows:
01 = time slot 1
10 = time slot 2
11 = time slot 3
0x12
0x24
7—6
5
RBUSMODE
4
3
RBUSPOS-1
RBUSPOS-0
2
TBUSMODE
1
0
TBUSPOS-1
TBUSPOS-0
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