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| 型號： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 57/90頁 |
| 文件大小： | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
43
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Table 15
.
Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits
(continued)
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0x09
—
7
—
The bits in register 0x09 are used to set up the test pattern.
TP_DS1E1N = 1 sets the frame sequence to DS1;
TP_DS1E1N = 0 sets the frame sequence to E1.
TP_INVERT = 1 forces the test pattern sequence to be
inverted.
When TPDROPSIDE = 1, the test pattern is dropped from
the SPE drop logic. The DS1/E1 output that is dropped is
described in the Microprocessor Interface Description (con-
tinued) section on page 50. When TPDROPSIDE = 0, the
DS1/E1 that is dropped is the same as described in the
DS1/E1 Insertion Selection section on page 47.
The TPDROP[4:0] bits are used to select the VT that needs
to be dropped.
TP_DS1E1N
6
TP_INVERT
5
TPDROPSIDE
4
3
2
1
0
—
TPDROP-4
TPDROP-3
TPDROP-2
TPDROP-1
TPDROP-0
—
0x0A
The bits in register 0x0A indicate the condition of the test
pattern detector.
If the test pattern detector has been able to synchronize on
the dropped signal, then TPOOS = 0.
When TPOOS = 0, then the TPERR-[6:0] bits are used to
keep count of the number of bit errors the test pattern
detector has seen. This error count is cleared when the
register is read by the microprocessor.
0x80
7
TPOOS
6
5
4
3
2
1
0
TPERR-6
TPERR-5
TPERR-4
TPERR-3
TPERR-2
TPERR-1
TPERR-0
F2-[7:0]
0x0B
7—0
The F2-[7:0] bits in register 0x0B are used to report the F2
receive byte in the path overhead.
The C2-[7:0] bits in register 0x0C are used to report the
received C2 label byte in the path overhead. The default
value for this register indicates path unequipped.
0x00
0x0C
7—0
C2-[7:0]
0x00
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