Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
38
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Table 15
.
Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits
(continued)
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0x01
—
—
The bits in register 0x01 are used to provision device-level
control bits. The functions of these bits are described
below.
REI_Enable. When REI_EN = 1, the device will automati-
cally insert the appropriate REI into the transmitted Z2, G1,
V5 overhead bytes whenever it receives BIP errors. If
REI_EN = 0, then the automatic insertion of REI is dis-
abled.
When AUTO_LRDI = 1, the device will automatically insert
line RDI.
When TXPAISINS = 1, the device will write all 1s into the
pointer bytes (H1—H3) and all of the synchronous payload
envelope (SPE).
The DJACTL is used to enable the use of the built-in digital
jitter attenuators. When DJACTL = 0, the gapped DS1/E1
clock and data are transmitted by the device; otherwise,
the smoothed clock and data are transmitted.
Reserved.
STS-1_Scramble. When STS1SCR = 1, the device scram-
bles the outgoing STS-1 frame according to the SONET
frame synchronous scrambling sequence 1 + x
6
+ x
7
. The
sequence is reset to 1111111 at the beginning of the byte
following the C1 byte and scrambles all of the STS-1 data
except the A1, A2, and C1 bytes. When this bit is 0, then
the transmit data is not scrambled.
STS-1_Descramble. When STS1DSCR = 1, the device
descrambles the incoming STS-1 frame according to the
SONET frame synchronous descrambling sequence
1 + x
6
+ x
7
. The sequence is reset to 1111111 at the begin-
ning of the byte following the C1 byte and descrambles all
of the STS-1 data except the A1, A2, and C1 bytes. When
this bit is 0, then the received data is not descrambled.
STS-1_Loopback. When STS1LB = 1, the transmitted data
is looped back to the receive side. When this bit is 0, the
device uses the received data.
7
REI_EN
6
AUTO_LRDI
5
TXPAISINS
4
DJACTL
3
2
—
STS1SCR
1
STS1DSCR
0
STS1LB