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| 型號： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 51/90頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
37
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
Hexadecimal notation is used in both the Address and the Reset Default columns in all the register description
tables in this section.
Device-Level Control, Alarm, and Mask Bits (0x00—0x16)
Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0x00
—
—
The bits in the register 0x00 are used for device-level con-
trol and error reporting.
Factory Test Mode. TEST_CNT = 1 forces all internal
counters to test mode and is intended for factory use only.
This bit should always be set to 0.
B1ERRINS, B2ERRINS, and B3ERRINS. B1ERRINS,
B2ERRINS, and B3ERRINS all cause continuous BIP-8
errors to be transmitted in their respective BIP-8 values.
7
TEST_CNT
6
5
4
3
B1ERRINS
B2ERRINS
B3ERRINS
LATCH_CNT
Latch Count. The device has a number of BIP, REI, and
pointer adjustment counters that are all updated when the
LATCH_CNT bit is written from 0 to 1. Nothing happens
when the bit is written from 1 to 0. The only internal counter
that is not updated by this bit is the test pattern counter.
The device can accept a blue signal clock at either the
exact DS1 rate (BLUECLKSEL = 0), or at 16 times the DS1
rate (BLUECLKSEL = 1).
BIP Error Counter or BIP Block Counter. The
BIPBLKCNT bit is used to determine whether the BIP
counters count the number of BIP errors (BIPBLKCNT = 0)
or the number of BIP blocks that contain errors
(BIPBLKCNT = 1).
Reserved.
2
BLUECLKSEL
1
BIPBLKCNT
0
—
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