參數(shù)資料
型號(hào)： TMPR28051
英文描述： TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述： TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢
文件頁(yè)數(shù)： 54/90頁(yè)
文件大?。?/td> 1090K
代理商： TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
40
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Table 15
.
Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits
(continued)
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0x03
—
—
The bits in register 0x03 are used to report problems at the
receive STS-1 level.
The device monitors the received J1 byte for path trace
mismatches. When the received J1 byte pattern does not
match the previously received pattern, then TRACEER = 1.
This is an event bit and is held until read.
RXPARER = 1 reports a parity violation on the receive
STS-1 data bus when in parallel mode. This is an event bit
and is held until read.
Reserved.
The device monitors the incoming H4 byte for loss of multi-
frame indication (H4LOMF = 1). This is an event bit and is
held until read.
STS1PAIS = 1 reports path AIS as detected by the receive
pointer interpreter. This is a current state bit with a mini-
mum persistence of 375
μ
s. The indications reset if the
condition is no longer true.
STS1LOP = 1 reports a loss of STS-1 pointer. This is a cur-
rent state bit with a minimum persistence of 125
μ
s. The
indications reset if the condition is no longer true.
STS1LOF = 1 reports an out of frame condition that per-
sists for more than 3 ms. This is a current state bit with a
minimum persistence of 3 ms. The indications reset if the
condition is no longer true.
STS1OOF = 1 reports an out of frame condition on the
receive STS-1 signal. This is a current state bit with a mini-
mum persistence of 500
μ
s. The indications reset if the
condition is no longer true.
The bits in register 0x04 are used to mask the contributions
of the bits in register 0x03 to the microprocessor interrupt
output, INT. When any of these bits are at a logic 1 level,
the corresponding bit in register 0x03 is masked from con-
tributing to the output interrupt. The reset default for this
register masks all of the bits in register 0x03.
7
TRACEER
6
RXPARER
5
4
—
H4LOMF
3
STS1PAIS
2
STS1LOP
1
STS1LOF
0
STS1OOF
0x04
7
6
5
4
3
2
1
0
TRACEERMSK
RXPARERMSK
—
H4LOMFMSK
STS1PAISMSK
STS1LOPMSK
STS1LOFMSK
STS1OOFMSK
Bit 5 is reserved.
0xFF
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