參數(shù)資料
型號(hào)： TMPR28051
英文描述： TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述： TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢
文件頁(yè)數(shù)： 28/90頁(yè)
文件大小： 1090K
代理商： TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
14
Lucent Technologies Inc.
DS1/E1 to STS-1 Block Descriptions
(continued)
STS-1/AU-3 Generate
(continued)
Path remote error indicator (REI-P) reports the number
of remote errors. The four REI-P
bits contain the num-
ber of B3 BIP-8 errors detected in the current frame
when REI_EN = 1 (bit 7 of register 0x01). Valid values
for these 4 bits are 0000—1000. The path remote
defect indicator (RDI-P) bits report back such condi-
tions as receive AIS-P, signal failure, and path trace
mismatch. These bits, 5 through 8 of the G1 byte
(G1INS-[5:8] in register 0x11), are user programmable
by the microprocessor and are
not
inserted automati-
cally by the device.
The H4 byte is inserted using the reduced H4 coding
sequence format, where the 6 most significant bits are
ones, and the 2 least significant bits take on the follow-
ing values: 00-01-10-11-00, etc. The value of 00 indi-
cates that the next STS-1 SPE contains the V1
overhead byte.
The STS-1 can be provisioned to send AIS-P
(TXPAISINS = 1 in bit 5 of register 0x01). Writing AIS-P
consists of writing all 1s into the H1—H3 bytes and the
entire SPE.
The transmitted STS-1 can be configured to scramble
the output data (STS1SCR = 1 in bit 2 of register 0x01)
or transmit the data without scrambling (STS1SCR = 0
in bit 2, register 0x01). It is useful to turn off SONET
scrambling if the data is going to be immediately multi-
plexed into a higher rate SONET signal. When
STS1SCR = 1 in register 0x01, the device scrambles
the outgoing STS-1 frame according to the SONET
frame synchronous scrambling sequence 1 + x
6
+ x
7
.
The sequence is reset to 1111111 at the beginning of
the byte following the C1 byte and scrambles all of the
STS-1 data except the A1, A2, and C1 bytes. When
this bit is 0, then the transmit data is not scrambled by
the device.
SPE Insertion Logic
In addition to the one column of path overhead and 84
columns of VT payload, the STS-1 SPE also contains
two columns of fixed stuff bytes. The path overhead is
located in column #1, while column #30 and column
#59 contain the fixed stuff bytes. The remaining col-
umns contain the interleaved VT data as shown in
Table 8.
The SPE insertion logic block acts in conjunction with
the STS-1 frame generate block to place the VT infor-
mation in the transmitted data stream.
The cross-referencing between the VT1.5 # listed in
Table 8 and the standard format (VT Group #, VT #)
listed in GR-253-CORE section 3.2.4 is shown in
Table 9.
The cross-referencing between the VT2 # listed in
Table 10 and the standard format (VT Group #, VT #)
listed in GR-253-CORE section 3.2.4 is shown in
Table 11.
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