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參數(shù)資料
| 型號(hào)： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 27/90頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
13
Lucent Technologies Inc.
DS1/E1 to STS-1 Block Descriptions
(continued)
VT Generate
(continued)
The device would transmit 0 in each of the O bits when
the DS1_E1N pin is pulled high. If DS1_E1N is pulled
low, the device will transmit 1 in each of the O bits.
The R bits are always set to 1.
The device transmits all 1s in the J2, Z6/N2, and Z7/K4
bytes.
The device can be configured such that any detected
BIP-2 errors in the VT receive side result in REI-V
being written into the corresponding transmit VT slot
(when REI_EN = 1 in bit 7 of register 0x01).
STS-1/AU-3 Generate
The device generates an STS-1 signal based on an
incoming clock (TSTS1CLK) and frame sync pulse
(TSTS1SYNC). The frame sync pulse can be a single
clock-period wide to indicate an 8 kHz sync, or it can
contain pulses in three clock periods to indicate a com-
posite 2 kHz sync. (See the Transmit Sync Timing sec-
tion, page 70.)
The STS-1 frame is 9 rows x 90 columns that repeats
at an 8 kHz rate. Each column is 1-byte wide. The
STS-1 frame contains three columns of transport over-
head, one column of path overhead, and 86 columns of
payload.
The 36 bytes of STS-1 overhead are allocated as
shown in Table 6.
Table 6. STS-1 Overhead Byte Allocation
The overhead bytes that are inserted by the device are
described below. All of the remaining overhead bytes
are given a fixed value of all 0s when DS1_E1N (bit 0
in register 0x07) is high, or all 1s when DS1_E1N is
low.
The device inserts the correct frame pattern of 0xF628
into the A1 and A2 bytes.
The device inserts a fixed value of 0x01 into the J0
byte.
The device generates and inserts valid B1, B2, and B3
BIP-8 even parity bytes into the STS-1 overhead.
These bytes are forced to odd parity when
B[1:3]ERRINS = 1 in bit 6 through bit 4 of register 0x00.
The device will provide an STS-1 pointer with a fixed
value of 522 (decimal) with 0110 in the new data flag
(NDF) bits. The SS bits are determined by the level of
the DS1_E1N pin. When this pin is high, the device
puts 00 in the SS bits. When this pin is low, the device
puts 10 in the SS bits. This pointer value indicates that
the J1 path overhead byte follows immediately after the
J0 line overhead byte.
The J1 byte is used for path trace. This byte repetitively
transmits a 64-byte fixed length sequence to verify
end-to-end connectivity. These 64 bytes are program-
mable by the microprocessor by provisioning
TJ1BYTE[7:0]_[64:1] in registers 0xC0—0xFF (when
TJ1BYTE = 1 in register 0xBF). The method for pro-
gramming these bits is described in detail in the regis-
ter description of the transmit J1 path trace bytes,
page 59.
The F2 byte can be provisioned by the microprocessor
(F2INS-[7:0]) in register 0x10.
The device inserts a value of 0x02 into the C2 byte,
indicating VT structured STS-1 SPE.
The three least significant bits of the K2 byte can be
provisioned by the microprocessor (K2INS-[6:8]) in reg-
ister 0x11.
The four least significant bits of the S1 byte can be pro-
visioned by the microprocessor (S1INS-[3:0]) in regis-
ter 0x13.
The M0 byte is used to report B2 line REI (REI-L) when
REI_EN = 1 in register 0x01. This register contains the
number of B2 BIP-8 errors detected in the current
receive frame circuitry when REI_EN = 1 (bit 7 0f regis-
ter 0x01). Valid values for these 4 bits are 0000—1000.
The G1 byte is used to convey path condition and per-
formance back to the far end. The format of the G1
byte is shown in Table 7.
Table 7. G1 Path Condition/Performance Byte
Format
Col. 1
A1
B1
D1
H1
B2
D4
D7
D10
S1
Col. 2
A2
E1
D2
H2
K1
D5
D8
D11
M0
Col. 3
J0
F1
D3
H3
K2
D6
D9
D12
E2
Col. 4
J1
B3
C2
G1
F2
H4
Z3/F3
Z4/K3
Z5/N1
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 9
Bit #
1
2
REI-P
3
4
5
6
7
8
User-Provisioned
RDI-P
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