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| 型號： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 70/90頁 |
| 文件大小： | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
56
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Block Control (0xBF)
Table 26. Register 0xBF: Block Control
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0xBF
—
—
The bits in register 0xBF control the information presented
to the microprocessor from the registers 0xC0—0xFF.
These last 64 bytes will display different results depending
on the value programmed into this byte. A hierarchy of
evaluation of these bytes occurs in the following three ways
presented in the description of bits 2, 1, 0.
Reserved. These bits are set to 0.
If TJ1BYTE = 1, the transmitted J1 byte values are pre-
sented. These registers are read/write. Any values written
into these registers will change the J1 byte values that are
transmitted.
If RJ1BYTE = 1, the received J1 bytes are presented
(read only).
If REI_CNTS = 1, REI error information is presented
(read only).
If BIP_CNTS = 1, BIP error information is presented,
regardless of the values of the other bits in this register
(read only).
7—4
3
—
TJ1BYTE
2
RJ1BYTE
1
REI_CNTS
0
BIP_CNTS
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