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| 型號： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 56/90頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
42
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Table 15
.
Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits
(continued)
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0xFF
0x06
7
6
5
4
3
2
1
0
ESOFMSK
VTSIZEMSK
VTLOPMSK
VTRFIRDIMSK
VTAISMSK
VTLABMSK
AISLOCMSK
STS1LOSMSK
The bits in register 0x06 are used to mask the contributions
of the bits in register 0x05 to the microprocessor interrupt
output, INT. When any of these bits is 1, the corresponding
bit in register 0x05 is masked from contributing to the out-
put interrupt. The reset default for this register masks all of
the bits in register 0x05.
0x07
This register reports the hardware selected device mode.
Reserved. These bits are set to 0 at reset.
This bit reports the DS1_E1N value from the device input
pin.
The bits in register 0x08 are used to configure the test pat-
tern generator and detector.
A 0 to 1 transition on LATCH_TP causes the running error
count to be latched and presented to the microprocessor.
RCV_FRAME = 1 causes a framed test pattern to be
expected; a 0 causes an unframed test pattern to be
expected.
RCV_PAT[1:0] determines the receive test pattern
sequence where 00 = QRSS, 01 = 2
23
– 1,
10 = 2
20
– 1, 11 = 2
15
– 1.
ERROR_INS causes a single error to be inserted in the
data (not frame) bits after a 0 to 1 transition.
XMT_FRAME = 1 causes a framed test pattern to be gen-
erated; a 0 causes an unframed test pattern to be gener-
ated.
XMTPAT-[1:0] determines the transmit test pattern
sequence where 00 = QRSS, 01 = 2
23
– 1,
10 = 2
20
– 1, 11 = 2
15
– 1.
0x01
7—1
0
—
DS1_E1N
0x08
0x00
7
LATCH_TP
6
RCV_FRAME
5
4
RCV_PAT-1
RCV_PAT-0
3
ERROR_INS
2
XMT_FRAME
1
0
XMT_PAT-1
XMT_PAT-0
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