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參數(shù)資料
| 型號(hào)： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁(yè)數(shù)： | 53/90頁(yè) |
| 文件大?。?/td> | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
39
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Table 15
.
Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits
(continued)
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0x02
—
—
The bits in register 0x02 are used to set the edges that
retime data into and out of the device.
Receive Serial Data, Transmit Serial Data. Both the
RXSERIAL and TXSERIAL bits are used to set the type of
STS-1 data. When either serial bit is written to 1, the STS-1
rail runs in serial mode; otherwise, the STS-1 rail runs in
parallel mode.
Both the RXPARITY and TXPARITY bits determine the
type of parity for data buses. When these bits are written
with 1, odd parity is used; otherwise, even parity is used.
When the edge register bits are set to 1, the data is retimed
(either in or out) by the rising clock edge; when set to a
logic 0, the data is retimed by the falling clock edge. Note
that the TSTS1SERIAL data always comes out on the ris-
ing edge of the TSTS1CLKOUT.
7
6
RXSERIAL
TXSERIAL
5
4
RXPARITY
TXPARITY
3
2
1
0
RXSTS1EDGE
TXSTS1EDGE
RXDS1EDGE
TXDS1EDGE
Note:
The TXSTS1EDGE (bit 2) should always be set to 0
to avoid potential race condition inside the device.
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