參數(shù)資料
型號(hào)： TMPR28051
英文描述： TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述： TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢
文件頁(yè)數(shù)： 72/90頁(yè)
文件大?。?/td> 1090K
代理商： TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
58
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Detected REI Errors (0xC0—0xFD)
Table 29. Registers 0xC0—0xFD: Detected REI Errors
Note:
Bits in registers 0xC0—0xFF can have one of four configurations, depending upon the setting of register
0xBF. When register 0xBF is set for BIP_CNTS = 0
and
REI_CNTS = 1, the bytes in registers 0xC0—0xFD
are used to count the number of REI errors detected by the device.
* These registers are not contiguous, i.e., every other register in this group is shown (0xC6, 0xC8, 0xCA, . . . 0xFC) per the register map, page
31 and page 32.
These registers are not contiguous, i.e., every other register in this group is shown (0xC7, 0xC9, 0xCB, . . . 0xFD) per the register map, page
31 and page 32.
Table 30. Registers 0xFE—0xFF: Reserved
When register 0xBF is set for BIP_CNTS = 0
and
REI_CNTS = 1, the bytes in registers 0xFE—0xFF are reserved.
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
Value is
0.
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6—
0xFC*
7—0
7—0
7—0
7—0
7—0
7—0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
—
Reserved. These bits are set to 0.
B2REI-[15:8]
B2REI-[7:0]
B3REI-[15:8]
B3REI-[7:0]
VT[1:28]PTR–3
VT[1:28]PTR–2
VT[1:28]PTR–1
VT[1:28]PTR–0
—
VTREI10_[1:28]
VTREI9_[1:28]
VTREI8_[1:28]
VTREI7_[1:28]
VTREI6_[1:28]
VTREI5_[1:28]
VTREI4_[1:28]
VTREI3_[1:28]
VTREI2_[1:28]
VTREI1_[1:28]
VTREI0_[1:28]
Registers 0xC2—0xC5. The registers, 0xC2—0xC5, are
the REI errors detected by B2 and B3 (see the STS-1/AU-3
Terminate section, page 16 and page 17).
Registers 0xC6—0xFD. The remaining registers in the
block indicate the errors seen by the REI error detectors in
the individual VT1.5 slots. Since the VT REI errors only
require 11 bits, the VT pointer decrement counts are also
presented in these registers. The values in all of these
counters is latched by the LATCH_CNT bit
(bit 3) in register 0x00. (See the STS-1/AU-3 Terminate
section, page 16 and page 17.)
Note:
In registers 0xC6—0xFC, bit 3 is reserved.
0xC7—
0xFD
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0x00
0xFE
0xFF
7—0
7—0
—
Reserved. These bits are set to 0.
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