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| 型號(hào)： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 22/90頁 |
| 文件大小： | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
8
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* I
u
indicates an internal pull-up; I
d
indicates an internal pull-down. All I/O not explicitly stated with a buffer type are 5 V TTL compatible; they will
tolerate 5 V at their inputs.
Pin
179
Symbol
MPMUX
Type*
I
Name/Description
Microprocessor Multiplex Mode.
Setting MPMUX = 1 allows the micropro-
cessor interface to accept the multiplexed address and data signals. Setting
MPMUX = 0 allows the microprocessor interface to accept demultiplexed
(separate) address and data signals.
Microprocessor Mode.
When MPMODE = 1, the device uses the address
latch enable type microprocessor read/write protocol with separate read and
write controls. Setting MPMODE = 0 allows the device to use the address
strobe type microprocessor read/write protocol with a separate data strobe
and a combined read/write control.
Read (Active-Low).
If MPMODE = 1, this pin is asserted low by the micropro-
cessor to initiate a read cycle.
Read/Write.
If MPMODE = 0, this pin is asserted high by the microprocessor
to indicate a read cycle or asserted low to indicate a write cycle.
Address Latch Enable.
If MPMODE = 1, this pin becomes the address latch
enable for the microprocessor. When this pin transitions from high to low, the
address bus inputs are latched into the internal registers.
Address Strobe (Active-Low).
If MPMODE = 0, this pin becomes the
address strobe for the microprocessor. When this pin transitions from high to
low, the address bus inputs are latched into the internal registers.
Chip Select (Active-Low).
This pin is asserted low by the microprocessor to
enable the microprocessor interface (see Microprocessor Configuration
Modes section on page 20). This pin has an internal 100 k
pull-up resistor.
Interrupt.
This pin is asserted high to indicate an interrupt produced by an
alarm condition in register 3 or 5. The activation of this pin can be masked by
microprocessor registers 4 and 6.
Ready.
If MPMODE = 1, this pin is asserted high to indicate the device has
completed a read or write operation. This pin is in a high-impedance state
when CS is high.
Data Transfer Acknowledge (Active-Low).
If MPMODE = 0, this pin is
asserted low to indicate the device has completed a read or write operation.
Microprocessor Interface Address/Data Bus.
If MPMUX = 0, these pins
become the bidirectional, 3-statable data bus. If MPMUX = 1, these pins
become the multiplexed address/data bus.
Microprocessor Interface Address.
If MPMUX = 0, these pins become the
address bus for the microprocessor interface registers.
Write (Active-Low).
If MPMODE = 1, this pin is asserted low by the micro-
processor to initiate a write cycle.
Data Strobe (Active-Low).
If MPMODE = 0, this pin becomes the data
strobe for the microprocessor. When R/W = 0 (write), a low applied to this pin
latches the signal on the data bus into internal registers.
Hardware Reset (Active-Low).
If RESET is forced low, all internal states in
the transceiver paths are reset and data flow through each channel will be
interrupted (see Device-Level Control, Alarm, and Mask Bits (0x00—0x16)
section on page 37). This pin has an internal 20 k
pull-up resistor.
Boundary-Scan Clock.
This pin has an internal 20 k
pull-up resistor.
180
MPMODE
I
181
RD_R/W
I
178
ALE_AS
I
87
CS
I
u
86
INT
O
183
RDY_DTACK
O
48—50,
55—59
AD[7:0]
I/O
60—64,
66—68
176
A[7:0]
I
WR_DS
I
106
RESET
I
u
184
TCK
I
u
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