參數(shù)資料
型號(hào)： TMPR28051
英文描述： TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述： TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢
文件頁(yè)數(shù)： 31/90頁(yè)
文件大?。?/td> 1090K
代理商： TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
17
Lucent Technologies Inc.
STS-1 to DS1/E1 Block Descriptions
(continued)
STS-1/AU-3 Terminate
(continued)
All of the internal counters have the ability to store
more than one second of counts. As long as the
LATCH_CNT (bit 3) in register 0x00 occurs every sec-
ond or faster, no counts will be lost. In case this does
not happen, all of the running counters will hold their
maximum value rather than roll over to zeros.
The device performs pointer interpretation on the
incoming signal to locate the start of the SPE. The
pointer interpretation block will indicate when the
device is in the path loss of pointer (LOP-P) or path AIS
(AIS-P) condition.
Loss of pointer condition is declared as the result of
either of the following conditions:
1. Continuous NDF—If the device receives 1001 in the
NDF field for nine consecutive frames, then LOP-P
is declared.
2. Invalid pointer values—If the device receives nine
frames consecutively of a pointer that is not a nor-
mal value, NDF, AIS-P, increment, or decrement,
then LOP-P is declared. The SS bits do not contrib-
ute to LOP-P when DS1_E1N is high; otherwise, a
non-10 value in the SS bits
will
contribute to
LOP-P.
AIS-P is declared on three consecutive frames with all
1s in the H1 and H2 bytes.
AIS-P and LOP-P are mutually exclusive conditions. If
neither STS1PAIS (bit 3 in register 0x03) or STS1LOP
(bit 2 in register 0x03) is a logic 1, then the pointer
interpreter declares a normal pointer. As part of the
normal operation, the device will respond appropriately
to valid NDF, increment, and decrement indications.
Increment and decrement operations will be counted
by the device and presented to the microprocessor via
the SPTR+[7:0] and SPTR–[7:0] bits in registers 0xFE
and 0xFF, respectively.
The B1, B2, and B3 BIP-8 values are recalculated and
compared to the received values. Any differences are
counted by the appropriate error counter
(B[1:3]BIPCNT-[15:0] in registers 0xC0—0xC5 when
BIP_CNTS = 1 in register 0xBF). In addition, B2 and
B3 REI errors are also counted in registers
0xC2—0xC5 (B[2:3]REI-[15:0]; register 0xBF settings:
REI_CNTS = 1 and BIP_CNTS = 0). The running and
latched counts for both B1 and B2 counters are held at
zero during OOF. The running and latched counts for
B3 counters are held at zero during OOF as well as
LOP-P.
The device can be provisioned to count bits in error
(BIPBLKCNT = 0 in bit 1 of register 0x00) or blocks in
error (BIPBLKCNT = 1 in bit 0 of register 0x00).
The J1 byte is terminated within the device. This con-
sists of writing the receive J1 sequentially in a 64-byte
register (modulo 64).
At start-up, the receive J1 byte register is all 0s. When-
ever the received J1 byte value does not match the
current J1 byte in the register, the path trace mismatch
TRACEER bit (bit 7 in register 0x03) is set to logic 1.
This allows the user to read the 64-byte register once,
and then ignore it unless differences are received.
TRACEER bit (bit 7 in register 0x03) is masked during
AIS-P and LOP-P.
The F2 byte (F2-[7:0] in register 0x0B), the C2 byte
(C2-[7:0] in register 0x0C), the 3 least significant bits of
the K2 byte (K2-[6:8] in register 0x0D), the 4 least sig-
nificant bits of the S1 byte (S1-[3:0] in register 0x14),
and the 4 least significant bits of the G1 byte (G1-[5:8]
in register 0x0D) are monitored by the microprocessor.
The number of consistent, consecutive frames to
update the values of all of these monitored bytes can
be set by the user to anywhere between 2 and 15
frames (F2#DET-[3:0] in register 0x0E, C2#DET-[3:0]
in register 0x0E, K2#DET-[3:0] in register 0x0F,
G1#DET-[3:0] in register 0x0F). None of these regis-
ters will update during OOF condition.
SPE Drop Logic
The SPE drop logic uses the H4 multiframe indicator to
identify the V1 byte and drop the data to the correct VT
termination blocks. Loss of multiframe synchronization
will be reported to the microprocessor (H4LOMF = 1 in
bit 4 of register 0x03).
VT Terminate
The VT terminate block performs VT pointer interpreta-
tion on the received signal to locate the VT overhead.
LOP-V (VTLOP[1:28] bit 6 in registers 0x6B—0x86)
and AIS-V (VTAIS[1:28] bit 3 in registers 0x6B—0x86)
are reported to the microprocessor. LOP-V is declared
as a result of either of the following conditions:
1. Continuous NDF—If the device receives 1001 in the
NDF field for nine consecutive superframes, then
LOP-V is declared.
2. Invalid pointer values—If the device receives nine
frames consecutively of a pointer that is not a nor-
mal value, NDF, AIS-V, increment, or decrement,
then LOP-V is declared. The SS bits
do
contribute
to LOP-V.
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