參數(shù)資料
型號： TMPR28051
英文描述： TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述： TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢
文件頁數(shù)： 33/90頁
文件大?。?/td> 1090K
代理商： TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
19
Lucent Technologies Inc.
Test Pattern Block Descriptions
The device contains a test pattern generator and a test
pattern detector for use in maintenance and trouble-
shooting.
Test Pattern Insert
The test pattern generator is capable of transmitting
four different test patterns (XMT_PAT-[1:0] in bit posi-
tions 0 and 1 of register 0x08). In addition to a 2
15
– 1,
a 2
20
– 1, and a 2
23
– 1 sequence, the device can also
transmit a QRSS sequence. The QRSS pattern is a
2
20
– 1 pseudorandom bit sequence defined by the
equation 1 + x
17
+ x
20
= 0, with a 14 zero limit.
As can be seen in Figure 1 on page 5, this test pattern
can be inserted in the place of any of the transmitted
or
received DS1/E1 signals. The test pattern can also be
provisioned to be framed (XMT_FRAME = 1 in bit 2 of
register 0x08) or unframed (XMT_FRAME = 0 in bit 2
of register 0x08). The framed sequence can be either
DS1 SF format (TP_DS1E1N = 1 in bit 7 of register
0x09) or E1 format (TP_DS1E1N = 0 in bit 7 of register
0x09). The test pattern can also be forced to transmit a
bit error (ERROR_INS bit in register 0x08, bit position
3, is forced to make low to high transition). The test
patterns are O.151 compliant, so they can be used to
drive external test equipment as well as to perform
internal maintenance and troubleshooting.
Test Pattern Drop
The test pattern detector can detect the same four test
sequences generated by the test pattern generator
(RCV_PAT-[1:0] in bit positions 4 and 5 of register
0x08). When the detector is out of synchronization, the
device continuously monitors the input data signal for
matches with the expected data signal. When the
device detects 32 matches in a row, it declares itself in
sync (TPOOS = 0 in bit 7 of register 0x0A), and the
error detector is enabled. If the device detects eight
consecutive bit mismatches, the test pattern detector
declares itself out of sync (TPOOS = 1), and starts
searching again.
The test pattern detector can be configured to look for
a framed (RCV_FRAME = 1 in bit 6 of register 0x08) or
unframed (RCV_FRAME = 0 in bit 6 of register 0x08)
signal.
While in sync, the device counts the number of times
the input data differs from the expected data in a 7-bit
counter, TPERR-[6:0] (bit 0 through bit 6 in register
0x0A), that holds its count when it reaches the maxi-
mum value of 128. This counter is reset when the
LATCH_TP bit (bit 7) in register 0x08 makes a 0 to 1
transition.
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