參數(shù)資料
型號: TMPR28051
英文描述: TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述: TMPR28051 STS-1/AU-3(的STM - 0)映射為版本的設(shè)備5設(shè)備咨詢
文件頁數(shù): 65/90頁
文件大小: 1090K
代理商: TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
51
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Tx VT Overhead Insertion Control (0x4F—0x6A)
Table 21. Registers 0x4F—0x6A: Tx VT Overhead Insertion Control
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
Value is
0.
0x4F—0x6A
The bits in these registers provision the transmitted VT
overhead byte, V5.
Each BIP2ERINS[1:28] bit = 1 forces the selected VT to
transmit inverted BIP-2 bits which causes the down-
stream receiver to declare continuous BIP-2 errors.
VTRFIRDIEN[1:28] The VTRFIRDIEN[1:28] bits control whether
RDI-V bits are inserted automatically by the device
(VTRFIRDIEN[1:28] = 1) or manually by the
microprocessor (VTRFIRDIEN[1:28] = 0).
VTRFIINS[1:28]
The VTRFIINS[1:28] bits directly program the transmitted
RFI-V bits when the corresponding VTRFIRDIEN[1:28]
bits = 1.
VTRDIINS[1:28]
The VTRDIINS[1:28] bits directly program the transmitted
RDI-V bits when the corresponding VTRFIRDIEN[1:28]
bits = 1.
VTAISINS[1:28]
Each VTAISINS[1:28] bit = 1 forces AIS-V to be written
into the corresponding VT slot. This consists of writing all
1s into the selected VT slot.
VTLABINS2_[1:28] The VTLABINS[2:0]_[1:28] bits directly program the
transmitted VT label bits. These bits are used to carry
unequipped information (VTLABINS[2:0]_[1:28] = 000) as
well as specific payload mappings and AIS-V.
7
BIP2ERINS[1:28]
6
5
4
3
2
1
0
VTLABINS1_[1:28]
VTLABINS0_[1:28]
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