參數(shù)資料
型號(hào)： TMPR28051
英文描述： TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述： TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢(xún)
文件頁(yè)數(shù)： 32/90頁(yè)
文件大?。?/td> 1090K
代理商： TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
18
Lucent Technologies Inc.
STS-1 to DS1/E1 Block Descriptions
(continued)
VT Terminate
(continued)
AIS-V is declared on three consecutive superframes
with all 1s in the V1 and V2 bytes.
AIS-V and LOP-V are mutually exclusive conditions. If
neither VTAIS[1:28] (bit 3 in registers 0x6B—0x86) or
VTLOP[1:28] (bit 6 in registers 0x6B—0x86) is a
logic 1, then the pointer interpreter declares a normal
pointer. As part of the normal operation, the device will
respond appropriately to valid NDF, increment, and
decrement indications. Increment and decrement oper-
ations will be counted by the device and presented to
the microprocessor via bits VT[1:28]PTR+[3:0] in regis-
ters 0xC6—0xFF (BIP_CNTS = 1), and via
VT[1:28]PTR–[3:0] in registers 0xC6—0xFF
(REI_CNTS = 1 and BIP_CNTS = 0), respectively.
Mismatches between the expected VT size bits, bit 11
for VT1.5 and bit 10 for VT2, and the actual received
SS size bits are reported to the microprocessor
VTSIZEER[1:28] bit (bit 7 in registers 0x6B—0x86).
Once the V5 byte is located, the device checks for
received BIP-2 errors (B2BIPCNT-[15:0] in registers
0xC0—0xC1 when BIP_CNTS bit in register 0xBF is
set to 1) and received REI (B[2:3]REI-[15:0] in registers
0xC2—0xC5 when REI_CNTS and BIP_CNTS in reg-
ister 0xBF are set to a 1 and 0, respectively). In addi-
tion to reporting the occurrence of BIP-2 errors and
REI, the device also maintains a count of each of these
on a per VT basis (VTREI[7:0]_[1:28] in registers
0xC7—0xFD: REI_CNTS = 1, BIP_CNTS = 0, and
BIP2CNT[7:0]_[1:28] in registers 0xC7—0xFD:
BIP_CNTS = 1). These running and latched counts for
both BIP-2 and REI counters are held at zero during
OOF, LOP-P, LOP-V, and AIS-V.
Additionally, the device checks for received RFI-V and
RDI-V (bit 5 and bit 4, respectively, in registers
0x6B—0x86) and received VT label
(VTLAB[2:0]_[1:28], bit 2 through bit 0 in registers
0x6B—0x86). Whenever the device receives three
consecutive consistent values for the VT label fields
that are different from the current values, it latches the
new value and reports the change to the microproces-
sor. When a 1 is received in VTRDI0_[1:28], bit 4 in
registers 0x6B—0x86 (represents bit 8 of the VT V5
overhead byte), for 10 consecutive superframes, it
declares an RDI-V condition.
Jitter Attenuate
Each of the 28 VTs has a built-in digital jitter attenuator
to remove the effects of mapping jitter and pointer
adjustment jitter. The bits in registers 0x8A—0x8F are
used to control various aspects of the digital jitter atten-
uator. Two programmable terms are used to set the
2nd-order loop damping factor and natural frequency of
the PLL. These terms are the gain threshold, set by
DJAGTHR[23:0] in registers 0x8D—0x8F, and scale
value, set by DJASCALE[15:0] in registers
0x8B—0x8C. The PLL bandwidth can be set using the
above registers to accommodate various system con-
straints.
The digital jitter attenuator block can be enabled by
setting the bit DJACTL = 1 (bit 4) in register 0x01.
These digital jitter attenuators require a blue signal
clock that runs at 16 times the nominal output rate.
The digital jitter attenuators are designed to meet cur-
rent jitter specifications as well as maximum time inter-
val error (MTIE) requirements. The clock transmitted
from this block nominally has a 50% duty cycle. The jit-
ter attenuator block can be bypassed by setting
DJACTL = 0 (bit 4) in register 0x01. If this block is
bypassed, the output produces gapped clock and data.
Drop Select Logic
Once the VT has been terminated, the source VT for
each DS1/E1 output is selected. This selection
requires 5 bits per slot to determine which VT to use by
programming VTDROP[4:0]_[1:28] bits (bits 4 through
0 in registers 0x33—0x4E). The numbering scheme for
the five provisioned bits ranges from 00001 to 11100,
where the binary value of the 5 bits corresponds to the
VT source. For instance, the value 00001 corresponds
to selecting VT Group 1, VT #1.
The unused values of 00000 and 11101—11110 will
cause AIS to be inserted for that DS1 output. By
default, all DS1/E1 outputs reset to a value of 00000 on
powerup, which causes all of the DS1/E1s to transmit
AIS (all 1s) using the blue signal clock.
The value of 11111 will insert the test pattern as
described next.
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