參數(shù)資料
型號(hào)： TMPR28051
英文描述： TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
中文描述： TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢
文件頁數(shù)： 21/90頁
文件大?。?/td> 1090K
代理商： TMPR28051
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
7
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
* I
u
indicates an internal pull-up; I
d
indicates an internal pull-down. All I/O not explicitly stated with a buffer type are 5 V TTL compatible; they will
tolerate 5 V at their inputs.
Pin
Symbol
TCLK[1:28]
Type*
O
Name/Description
47, 39, 38, 30,
29, 20, 19, 11,
10, 3, 206, 199,
198, 190, 175,
167, 166, 159,
154, 146, 145,
137, 136, 127,
126, 117, 115,
107
46, 41, 37, 32,
28, 22, 18, 13, 9,
4, 205, 200, 197,
191, 174, 169,
165, 160, 153,
147, 143, 138,
134, 128, 124,
118, 114, 108
45, 42, 36, 33,
27, 23, 17, 14, 8,
5, 204, 201, 195,
192, 173, 170,
164, 161, 152,
148, 142, 139,
133, 129, 123,
119, 113, 109
44, 43, 35, 34,
25, 24, 16, 15, 7,
6, 203, 202, 194,
193, 172, 171,
163, 162, 151,
149, 141, 140,
132, 131, 122,
120, 112, 110
102
Transmit DS1/E1 Clock.
DS1/E1 clock output. E1 signals can only
occupy TCLK[1:21].
TDATA[1:28]
O
Transmit DS1/E1 Data.
Transmit data output. E1 signals can only
occupy TDATA[1:21].
RCLK[1:28]
I
u
Receive DS1/E1 Clock.
Receive clock input. These pins have an
internal 20 k
pull-up resistor. E1 signals can only occupy RCLK[1:21].
RDATA[1:28]
I
u
Receive DS1/E1 Data.
Receive data input. These pins have an inter-
nal 20 k
pull-up resistor. E1 signals can only occupy RDATA[1:21].
DS1_E1N
I
DS1/E1 Input Identifier.
If this pin is pulled high, the device will default
to DS1 to STS-1 mode and transmit 0s in the unused overhead bytes
and 00 in the SS bits of H1. If pulled low, the device will default to E1 to
AU-3 mode and transmit 1s in the unused overhead bytes and 10 in
the SS bits of H1. This default selection can be overridden by setting
TOVERRIDE and ROVERRIDE bits in registers 0x88 (bit 0) and 0x89
(bit 0), respectively. The seven VT Groups can then be individually pro-
grammed to carry either DS1 (TVTG-1. . . 7 = 1, RVTG-1. . . 7 = 1) or
E1 (TVTG-1. . . 7 = 0, RVTG-1. . . 7 = 0) signals.
DS1 Blue Signal Clock.
In the event of a loss of input DS1 clock or an
unprovisioned DS1 output, this clock signal is used to generate the
DS1 blue signal (all 1s). This clock must be 1.544 MHz ± 32 ppm or 16
times this rate when using the digital jitter attenuator.
E1 Blue Signal Clock.
In the event of a loss of input E1 clock or an
unprovisioned E1 output, this clock signal is used to generate the E1
blue signal (all 1s). This clock must be 2.048 MHz ± 50 ppm or 16
times this rate when using the digital jitter attenuator.
101
DS1BLUECLK
I
208
E1BLUECLK
I
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