參數(shù)資料
型號(hào): 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 12/92頁
文件大?。?/td> 1352K
代理商: 21440
Introduction
1-4
21440 Multiport 10/100Mb/s Ethernet Controller
1.9
Hardware Overview
Table 1-1
describes the 21440 components.
Table 1-1. 21440 Components Description
Component
Description
Transmit FIFO
Handles the transmitted packets while taking care of retransmission in
case of collision. The transmit FIFO has direct interface to the FIFO bus.
Receive FIFO
Handles the received packets and supports packet deletion in case of
errors. The receive FIFO has direct interface to the FIFO bus.
Transmit MAC
Implements the IEEE 802.3 transmit MAC functions while interfacing
between the transmit FIFO and the front-end ENDEC, providing full MII
interface.
Receive MAC
Implements the IEEE 802.3 receive MAC functions while interfacing
between the front-end ENDEC through MII interface and the receive FIFO.
PCS
ENDEC implementing the 100BASE-X PCS layer, including the
100BASE-TX scrambler/descrambler function.
SNMP and RMON
Handles network statistic counters for SNMP and RMON.
Control
Handles the chip registers accessible through the CPU bus.
Clock Logic
Generates the clocks required by the chip.
JTAG
Includes the JTAG boundary scan logic.
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