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參數(shù)資料
| 型號： | 21440 |
| 廠商： | Intel Corp. |
| 英文描述： | Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器) |
| 中文描述： | 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器） |
| 文件頁數(shù)： | 59/92頁 |
| 文件大?。?/td> | 1352K |
| 代理商： | 21440 |
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Network Interface Operation
6-2
21440 Multiport 10/100Mb/s Ethernet Controller
6.2
MII Port Interface
In the MII mode (SER_MOD<SYP>=0), the MII/SYM port implements the IEEE 802.3 Standard
MII interface.
Table 6-1
describes the MII port signal names as they refer to the appropriate IEEE
802.3 signal names.
The MII management signals (mdc and mdio) are common to all eight ports.
Table 6-1
describes the MII port signals versus standard signals.
Table 6-1. MII Port Signals versus Standard Signals
MII Signals
IEEE 802.3 Signals
Purpose
tclk{i}
tx_clk
Transmit clock, synchronizes all transmit signals (ten{i}, txd{i}[3:0],
terr{i}). In the 100 Mb/s data rate, operates at 25 MHz. In the
10 Mb/s data rate, operates at 2.5 MHz.
rclk{i}
rx_clk
Receive clock, synchronizes all receive signals (dv{i}, rxd{i}[3:0],
rerr{i}). In the 100 Mb/s data rate, operates at 25 MHz. In the
10 Mb/s data rate, operates at 2.5 MHz.
ten{i}
tx_en
Transmit enable, asserted by the MAC sublayer when the first
transmit preamble nibble is driven over the MII. It remains asserted
for the remainder of the frame, up to the last CRC nibble.
txd{i}[3:0]
txd[3:0]
These lines provide transmit data, driving a nibble on each tclk{i}
cycle when ten{i} is asserted.
terr{i}
tx_err
Transmit error, asserted by the MAC layer to generate a coding
error on the nibble currently being transferred over txd{i}[3:0].
dv{i}
rx_dv
Receive data valid, asserted by the PHY layer when the first
received preamble nibble is driven over the MII. It remains asserted
for the remainder of the frame, up to the last CRC nibble.
rxd{i}[3:0]
rxd[3:0]
These lines provide receive data, driving a nibble on each rclk{i}
cycle when dv{i} is asserted.
rerr{i}
rx_err
Receive error, asserted by the PHY layer to indicate an error the
MAC cannot detect. If asserted during packet reception, indicates a
coding error on the frame currently being transferred on rxd{i}[3:0].
If asserted while dv{i} is deasserted with rxd{i}[3:0] equal to 1110,
indicates that a false carrier was detected by the PHY layer.
crs{i}
crs
Carrier sense, asserted by the PHY layer when either the transmit
or receive medium is active (not idle).
col{i}
col
Collision, asserted by the PHY layer when it detects a collision on
the medium. Remains asserted while this condition persists.
mdc
mdc
Management data clock, the mdio signal clock reference.
mdio
mdio
Management data input/output, used to transfer control signals
between the PHY layer and the manager entity. The 21440 is
capable of initiating control signal transfer between the 21440 and
the PHY devices.
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