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參數(shù)資料
| 型號(hào)： | 21440 |
| 廠商： | Intel Corp. |
| 英文描述： | Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器) |
| 中文描述： | 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器） |
| 文件頁數(shù)： | 54/92頁 |
| 文件大?。?/td> | 1352K |
| 代理商： | 21440 |
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21440 Multiport 10/100Mb/s Ethernet Controller
5-1
CPU Interface Operation
5
The following sections describe the CPU interface operation.
5.1
CPU Interface
The 21440 has a dedicated port for a CPU interface, enabling access to the different registers
without interfering with packet transfer through the FIFOs. The CPU interface is generic and
supports a wide range of standard controllers. Each of the eight 21440 ports has its own
independent registers. Each of the port registers is accessible through an 8-bit data bus and a 10-bit
address bus. A specific port is addressed by using the port select signals (cps[2:0]), which may be
considered a part of the address bus. Each port has a dedicated interrupt signal (cint_l) to report
special events to the CPU.
Each control and status register is 1 byte wide and accessible through a single CPU access.
Network statistic counters are multibyte wide and require multiple CPU accesses to be fully read.
5.2
Network Management
The 21440 includes network statistic counters defined by Ethernet SNMP MIB and RMON MIB
standards. Each event counter is 32 bits wide and each byte counter is 40 bits wide.
To assemble each counter value, its bytes must be read from the lower to the upper addresses.
Partial byte reading is also possible. If the exact counter value is not required, the lower counter
byte may not be read. If the counter is read often, the upper byte will always remain null and may
not be read.
Each counter is accessible through two different addresses. One address will cause the read byte to
reset, while the other will not. When a counter overflows, it remains stuck on the highest value it
has reached, and can generate an interrupt if programmed accordingly.
Receive statistic counters are updated according to analysis of the received packet, while ignoring
the 21440 filtering mode or the receive FIFO status. When the port is in the disable mode, the
counters are not updated.
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