viii
21440 Multiport 10/100Mb/s Ethernet Controller
Tables
1-1
2-1
2-2
2-3
3-1
3-2
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
6-1
6-2
6-3
6-4
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
9-1
A-1
21440 Components Description ..................................................................1-4
Signal Descriptions (Sheet 1 of 3) ................................................................2-1
21440 Pin Count...........................................................................................2-4
Pin List (Sheet 1 of 4)................................................................................2-5
CSR Register Mapping ................................................................................3-2
Network Statistic Register Mapping (Sheet 1 of 2)...................................3-22
Little Endian, 64-Bit Bus (BEND=0, BWID=1) ..............................................4-1
Little Endian, 32-Bit Bus (BEND=0, BWID=0) ..............................................4-1
Big Endian, 64-Bit Bus (BEND=1, BWID=1).................................................4-1
Big Endian, 32-Bit Bus (BEND=1, BWID=0).................................................4-1
FIFO Bus Receive Packet Status (Sheet 1 of 2) ..........................................4-5
SNMP MIB to 21440 Counters Mapping.......................................................5-2
RMON Statistics to 21440 Counters Mapping .............................................5-3
RMON Host to 21440 Counters Mapping ....................................................5-4
MII Port Signals versus Standard Signals ....................................................6-2
Ethernet Frame Description..........................................................................6-3
Flow control Field Matching..........................................................................6-8
SYM Port Signal Description ........................................................................6-9
Functional Operating Range.........................................................................8-1
3.3 V AC Signaling Specifications ................................................................8-1
5 V AC Signaling Specifications ...................................................................8-1
Absolute Maximum Rating............................................................................8-2
Supply Current and Power Dissipation.........................................................8-2
Temperature Limit Ratings ...........................................................................8-2
FIFO Bus Clock Timing Specifications .........................................................8-3
FIFO Bus 3.3 V Signaling Specifications......................................................8-3
FIFO Bus 5-V Signaling Specifications.........................................................8-4
FIFO Bus Signals Timing Specifications.......................................................8-4
CPU Port DC Specifications.........................................................................8-5
Timing Parameters .......................................................................................8-6
MII/SYM Port DC Specifications...................................................................8-7
MII/SYM Port Signals Timing Specifications.................................................8-7
Data Timing Parameters...............................................................................8-8
JTAG Port DC Specifications........................................................................8-9
JTAG Port Timing Specifications................................................................8-10
352-BGA Dimensional Attributes..................................................................9-2
Instructions Register.................................................................................... A-2