21440 Multiport 10/100Mb/s Ethernet Controller
iii
Contents
1
Introduction................................................................................................................1-1
1.1
General Description......................................................................................1-1
1.2
Integration Features......................................................................................1-1
1.3
FIFO Bus Features .......................................................................................1-1
1.4
Performance Features..................................................................................1-2
1.5
Serial Features..............................................................................................1-2
1.6
CPU Interface Features................................................................................1-2
1.7
Device Features............................................................................................1-3
1.8
21440 Block Diagram....................................................................................1-3
1.9
Hardware Overview ......................................................................................1-4
2
Pinout.........................................................................................................................2-1
2.1
Signal Description.........................................................................................2-1
2.2
Pin Count......................................................................................................2-4
2.3
Connection Rules..........................................................................................2-4
2.4
Pin List..........................................................................................................2-5
3
Register Descriptions.................................................................................................3-1
3.1
Register Conventions....................................................................................3-1
3.1.1
Access Rules...................................................................................3-1
3.2
CSR Register................................................................................................3-2
3.2.1
Register Mapping.............................................................................3-2
3.2.2
Base Registers.................................................................................3-3
3.2.2.1 Chip Interrupt Summary Register .......................................3-3
3.2.2.2 Interrupt Status Register.....................................................3-4
3.2.2.3 Interrupt Enable Register....................................................3-5
3.2.2.4 Transmit Status Register ....................................................3-6
3.2.2.5 Receive Status Register .....................................................3-7
3.2.2.6 Port Control Register ..........................................................3-8
3.2.2.7 Device ID Register..............................................................3-9
3.2.2.8 Revision ID Register ...........................................................3-9
3.2.2.9 Serial Command Register.................................................3-10
3.2.3
Configuration Registers .................................................................3-11
3.2.3.1 FIFO Threshold Register ..................................................3-11
3.2.3.2 FIFO Bus Mode Register ..................................................3-12
3.2.3.3 Transmit Parameters Register..........................................3-13
3.2.3.4 Transmit Error Mode Register...........................................3-14
3.2.3.5 Transmit Threshold and Backoff Register.........................3-15
3.2.3.6 Receive Parameters Register...........................................3-16
3.2.3.7 Receive Filtering Mode Register.......................................3-17
3.2.3.8 Transmit Pause Time Register .........................................3-18
3.2.3.9 Maximum Packet Size Register........................................3-18
3.2.3.10InterPacket Gap Register..................................................3-19
3.2.4
Serial Registers..............................................................................3-20
3.2.4.1 Serial Mode Register ........................................................3-20
3.2.4.2 Link Status Register..........................................................3-21
3.2.4.3 Physical Address Register................................................3-21
3.3
Network Statistic Counter Mapping.............................................................3-22
3.3.1
Register Mapping...........................................................................3-22