21440 Multiport 10/100Mb/s Ethernet Controller
vii
Figures
1-1
4-1
4-2
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
9-1
9-2
21440 Controller Block Diagram...................................................................1-3
Transmit Flow Diagram.................................................................................4-4
Receive Flow Diagram..................................................................................4-8
Transmit Start-of-Packet Timing ...................................................................7-1
Transmit End-of-Packet Timing ....................................................................7-2
Transmit FIFO Control Timing ......................................................................7-2
Transmit txrdy Timing ...................................................................................7-3
Receive Start-of-Packet Timing ....................................................................7-3
Receive End-of-Packet Timing .....................................................................7-4
Fastest Receive Reaccess After EOP..........................................................7-4
Receive rxfail Timing.....................................................................................7-5
Receive rxabt Timing....................................................................................7-5
Receive rxkep Timing ...................................................................................7-6
Receive Header Replay Timing ....................................................................7-6
Receive FIFO Control Timing .......................................................................7-6
Receive rxrdy Timing....................................................................................7-7
Consecutive Transmit-Transmit Timing........................................................7-7
Consecutive Transmit-Receive Timing.........................................................7-8
Consecutive Receive-Transmit Timing.........................................................7-8
Consecutive Receive-Receive Timing..........................................................7-8
Packet Transmission Timing.........................................................................7-9
Packet Reception Timing..............................................................................7-9
Transmission with Collision Timing...............................................................7-9
False Carrier Timing .....................................................................................7-9
FIFO Bus Clock Timing Diagram ..................................................................8-3
FIFO Bus Signals Timing Diagram ...............................................................8-4
CPU Port Read Timing Diagram...................................................................8-5
CPU Port Write Timing Diagram...................................................................8-6
MII/SYM Clock Timing Diagram....................................................................8-7
MII/SYM Port Transmit Timing Diagram .......................................................8-8
MII/SYM Port Receive Timing Diagram........................................................8-8
MII/SYM Port Carrier Sense and Collision Timing Diagram .........................8-8
JTAG Port Timing Diagram...........................................................................8-9
Part Marking.................................................................................................9-1
352-BGA Package - Bottom View.................................................................9-1