參數(shù)資料
型號(hào): 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁(yè)數(shù): 37/92頁(yè)
文件大?。?/td> 1352K
代理商: 21440
21440 Multiport 10/100Mb/s Ethernet Controller
3-17
Register Descriptions
3.2.3.7
Receive Filtering Mode Register
When a packet with a specific event is programmed to be passed, the corresponding packets are not
discarded and are transferred as regular packets. The status is reported in the receive status register
(RECV_STT) and can generate an interrupt according to the interrupt enable register (INT_EN).
If a specific event is not programmed to enable reception of a packet, the corresponding packets are
discarded from the receive FIFO. Failure will be reported onto the rxfail signal if the packet has
already started to be transferred onto the FIFO bus. If a packet with multiple errors is to be passed,
all corresponding bits must be set.
Bit Name
Bit Number
Bit Description
PFLC
7
Pass flow-control packets.
6
RESERVED
PMER
5
Pass packets with MII error.
PRTL
4
Pass too long packets.
PSRT
3
Pass short packets.
PDRB
2
Pass alignment error packets.
PCRC
1
Pass CRC error packets.
POVF
0
Pass FIFO overflow.
Access Rules
Register access
R/W
Value after reset
00H
相關(guān)PDF資料
PDF描述
21446 Net186-EVAL-KT? 24.9KB (PDF)
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