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參數(shù)資料
| 型號： | 21440 |
| 廠商： | Intel Corp. |
| 英文描述： | Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器) |
| 中文描述： | 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器） |
| 文件頁數(shù)： | 48/92頁 |
| 文件大?。?/td> | 1352K |
| 代理商： | 21440 |
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FIFO Interface Operation
4-2
21440 Multiport 10/100Mb/s Ethernet Controller
4.1.2
FIFO Status Signaling
The 21440 reports the status of each FIFO through dedicated signals. Each transmit FIFO has a
txrdy signal indicating that there is enough free space to load new data. Each receive FIFO has a
rxrdy signal indicating that there is enough data to be transferred onto the FIFO bus. The txrdy
signals are driven by the 21440 when the txctl_l signal is asserted, and the rxrdy signals are enabled
by the rxclt_l signal.The txrdy signal of a specific port is asserted when the txctl_l signal is asserted
and the specific port is selected (fps[2:0]). The same applies for the rxrdy signal of a specific port,
which is asserted with rxctl_l assertion and the specific port selection (fps[2:0]).
4.2
Packet Transmission
The following sections describe the packet transmission policy.
4.2.1
Packet Loading
The 21440 loads packets from the FIFO bus into the transmit FIFO during burst accesses. In order
to guarantee a minimal amount of data transfer, the transmit FIFO txrdy signal reports minimal
space availability according to a programmable threshold (FFO_TSHD<TTH>).
When a new packet is loaded in the FIFO, the first cycle of the first burst must be signalled with
sop signal assertion. If the txasis signal is asserted together with sop, the packet will be sent onto
the network without padding or CRC addition. At the end of a packet load, the last data must be
signalled with the assertion of the eop signal in the last cycle of the last burst. If the txerr signal is
asserted together with eop while sending the packet onto the network, the MII error signal terr will
be asserted and the CRC will be damaged if it was requested to be appended by the 21440.
Up to two packets can be loaded in the transmit FIFO, although the 21440 may be programmed to
handle only a single packet at a time (TX_PARAM<SPM>).
Byte masking signals (fbe_l[7:0]) may be used to load selective bytes. They can be used during
packet transfer to load packet segments on byte boundaries and for loading the exact number of
bytes at the end of a packet. Valid bytes may start at any byte boundary, while all valid bytes in a
given cycle need to be contiguous.
For example, a packet may be built up from the following buffers, with each one being transferred
in a different burst:
Buffer 1:
Buffer 2:
Buffer 3:
B3
B11
X
B2
B10
X
B1
B9
X
X
B8
X
X
B7
X
X
B6
X
X
B5
X
X
B4
B12
X
X
X
B14
B13
X
X
X
X
X
B19
X
B18
B21
B17
B20
B16
X
B15
X
X
X
X
X
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