參數(shù)資料
型號： 21440
廠商： Intel Corp.
英文描述： Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述： 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器）
文件頁數(shù)： 5/92頁
文件大?。?/td> 1352K
代理商： 21440
21440 Multiport 10/100Mb/s Ethernet Controller
v
6.5.5
MAC Full-Duplex Operation..........................................................................6-8
MAC Loopback Operations...........................................................................6-8
6.7.1
Internal Loopback Mode ..................................................................6-8
6.7.2
External Loopback Mode .................................................................6-9
SYM Mode....................................................................................................6-9
Flow Control.....................................................................................6-8
6.6
6.7
6.8
7
21440 Timing Diagrams.............................................................................................7-1
7.1
FIFO Bus Port Timing Diagrams...................................................................7-1
7.1.1
Transmit Start-of-Packet Timing ......................................................7-1
7.1.2
Transmit End-of-Packet Timing .......................................................7-2
7.1.3
Transmit FIFO Control Timing .........................................................7-2
7.1.4
Transmit Ready (txrdy) Timing.........................................................7-3
7.1.5
Receive Start-of-Packet Timing .......................................................7-3
7.1.6
Receive End-of-Packet Timing ........................................................7-4
7.1.7
Fastest Receive Reaccess after EOP..............................................7-4
7.1.8
Receive rxfail Timing........................................................................7-5
7.1.9
Receive rxabt Timing .......................................................................7-5
7.1.10 Receive rxkep Timing ......................................................................7-6
7.1.11 Receive Header Replay Timing .......................................................7-6
7.1.12 Receive FIFO Control Timing ..........................................................7-6
7.1.13 Receive Ready (rxrdy) Control Timing.............................................7-7
7.1.14 Consecutive Transmit-Transmit Timing ...........................................7-7
7.1.15 Consecutive Transmit-Receive Timing ............................................7-8
7.1.16 Consecutive Receive-Transmit Timing ............................................7-8
7.1.17 Consecutive Receive-Receive Timing .............................................7-8
7.2
MII/SYM Port Timing Diagrams ....................................................................7-8
7.2.1
Packet Transmission Timing............................................................7-9
7.2.2
Packet Reception Timing.................................................................7-9
7.2.3
Transmission with Collision Timing..................................................7-9
7.2.4
False Carrier Timing ........................................................................7-9
8
Electrical and Environmental Specifications..............................................................8-1
8.1
Functional Operating Range.........................................................................8-1
8.2
Absolute Maximum Rating............................................................................8-1
8.3
Supply Current and Power Dissipation.........................................................8-2
8.4
Temperature Limit Ratings............................................................................8-2
8.5
Reset Specification.......................................................................................8-2
8.6
FIFO Port Specifications...............................................................................8-3
8.6.1
Clock Specification...........................................................................8-3
8.6.2
3.3 Volt DC Specifications ...............................................................8-3
8.6.3
5 Volt DC Specifications ..................................................................8-4
8.6.4
FIFO Bus Signals Timing.................................................................8-4
8.7
CPU Port Specifications................................................................................8-5
8.7.1
DC Specifications.............................................................................8-5
8.7.2
Signals Timing .................................................................................8-5
8.7.2.1 Read Timing........................................................................8-5
8.7.2.2 Write Timing........................................................................8-6
8.7.2.3 Timing Parameters..............................................................8-6
8.8
MII/SYM Port Specifications .........................................................................8-7
8.8.1
DC Specifications.............................................................................8-7
8.8.2
Signals Timing .................................................................................8-7
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