參數(shù)資料
型號: 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 36/92頁
文件大?。?/td> 1352K
代理商: 21440
Register Descriptions
3-16
21440 Multiport 10/100Mb/s Ethernet Controller
3.2.3.6
Receive Parameters Register
The receive parameters register defines the receive data flow on the FIFO bus.
Bit Name
Bit Number
Bit Description
CRCR
7
CRC remove.
When set, the last four bytes of the received packet will not be transferred
onto the FIFO bus. Packets shorter than 4 bytes will cause invalid data to
appear on the FIFO bus.
HRPL
6
Header replay.
When set, packet header is transferred twice onto the FIFO bus. If this bit is
set, the RX_FILT_MOD<PCRC> bit should be reset.
HDRS
5:0
Header size.
Header size is used for the header replay function and for rxrdy signal
assertion (even if the header replay function is disabled). The header size is
calculated in bytes as 4
×
HDRS (valid values: 4
HDRS
48).
Access Rules
Register access
R/W
Value after reset
10H
相關(guān)PDF資料
PDF描述
21446 Net186-EVAL-KT? 24.9KB (PDF)
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