參數(shù)資料
型號(hào)： 21440
廠商： Intel Corp.
英文描述： Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述： 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器）
文件頁(yè)數(shù)： 34/92頁(yè)
文件大小： 1352K
代理商： 21440
Register Descriptions
3-14
21440 Multiport 10/100Mb/s Ethernet Controller
3.2.3.4
Transmit Error Mode Register
The transmit error mode register controls the events that cause transmission stop. If, during packet
transmission, an error occurs and the corresponding bit is set, the transmit FIFO is flushed, and
transmission stops. The error is then reported in the transmit error status register (TERR_STT), and
can generate an interrupt according to the interrupt enable register (INT_EN).
Bit Name
Bit Number
Bit Description
—
7:3
RESERVED
XCLS
2
Stop transmission after excessive collisions.
When set, packet retransmission stops after 16 attempts. When reset, packets
will always be retransmitted following a collision until a successful
transmission is achieved.
LCLS
1
Stop transmission after late collision.
When set, transmission stops if a collision occurs after transmission of 64
bytes. When reset, the packet will be flushed from the transmit FIFO and the
following packet will be transmitted.
UNFS
0
Stop transmission after FIFO underflow.
When set, transmission stops if an underflow occurs after transmission of 64
bytes. When reset, the packet will be flushed from the transmit FIFO, and the
following packet will be transmitted.
Access Rules
Register access
R/W
Value after reset
00H
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