參數(shù)資料
型號: 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 50/92頁
文件大小: 1352K
代理商: 21440
FIFO Interface Operation
4-4
21440 Multiport 10/100Mb/s Ethernet Controller
4.2.6
Stopping Mode on Transmission Errors
If an error is programmed to cause the transmit process to stop, the 21440 will flush all the data
found in the transmit FIFO. The number of packets flushed from the transmit FIFO and the
transmission stop cause are reported in the transmit status register (TERR_STT). The subsequent
packets will be loaded only after the FIFO is restarted (PORT_CTR<TXSTT>).
Transmission errors may also generate an interrupt, if programmed to do so.
In the single-packet mode (TX_PARAM<SPM>), new packets are loaded into the transmit FIFO
only after successful transmit completion of the previous packet. In case of an error, only the
erroneous packet is flushed from the FIFO.
4.2.7
Transmit Flow Diagram
Figure 4-1
shows the transmit flow diagram.
Figure 4-1. Transmit Flow Diagram
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