參數(shù)資料
型號(hào): 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 33/92頁
文件大?。?/td> 1352K
代理商: 21440
21440 Multiport 10/100Mb/s Ethernet Controller
3-13
Register Descriptions
3.2.3.3
Transmit Parameters Register
The transmit parameters register handles the control of the transmit serial interface.
Bit Name
Bit Number
Bit Description
7:5
RESERVED
SPM
4
Single packet mode.
When set, a packet is loaded in the transmit FIFO only after the previous
packet was fully transmitted without any error.
XOND
3
XON disable.
When set, a flow-control packet will not be sent upon flct{i} signal
deassertion.
FLCE
2
Flow-control mode enable.
When set, transmission is stopped in the full-duplex mode while receiving
flow-control packets.
CRCD
1
CRC appending disable.
When set, packets are transmitted without padding or CRC appending to the
end of the packet. This field is ignored if the txasis signal is asserted during
the start of packet loading.
PADD
0
Padding appending disable.
When set, short packets are transmitted without the addition of bytes
complementing their sizes to 64 bytes. When the CRCD bit is set, this bit is
ignored. This field is ignored if the txasis signal is asserted during the start of
packet loading.
Access Rules
Register access
R/W
Value after reset
00H
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