參數(shù)資料
型號(hào)： 21440
廠商： Intel Corp.
英文描述： Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述： 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器）
文件頁(yè)數(shù)： 63/92頁(yè)
文件大?。?/td> 1352K
代理商： 21440
Network Interface Operation
6-6
21440 Multiport 10/100Mb/s Ethernet Controller
6.4.6
Backpressure
The 21440 provides the ability to prevent packet reception in the half-duplex mode. The
backpressure mode can be activated by programming (SER_COM<BKP>) or by asserting the
flct{i} signal. If any one of these is asserted, each receive activity detection triggers a transmit
activity that will cause a collision. This transmission consists of a 96-bit pattern. In the
backpressure mode, following a collision, the 21440 resends packets with minimal IPG and
without using the random backoff algorithm.
6.4.7
Flow Control
In the full-duplex mode, the 21440 supports the standard flow control defined in the IEEE 802.3
Standard, enabling the stopping of remote node transmissions. Upon triggering, the 21440 sends a
flow control frame in the following format:
The source address field (EA1
–
EA6) is taken from the PHY_ADD register.
Upon assertion of the flct{i} signal or setting of the flow control trigger bit (SER_COM<FCT>), a
flow control frame is sent with the pause time field (PT1
–
PT2) equal to the PAUSE_TIME
register. Upon deassertion, another flow control frame will be sent with the pause time field equal
to zero, meaning that the remote node may resume transmission. If the XON mode is disabled
(TX_PARAM<XOND>), the flow control frame will not be transmitted on deassertion. If the chip
is transmitting, the next flow control frame sent will be according to the last flow control trigger.
6.5
MAC Receive Operation
This section describes the detailed receive operation as supported by the 21440. Receive activities
are registered into network management registers, which are accessible through the CPU port.
6.5.1
Receive Initiation
The 21440 continuously monitors the network when reception is enabled. When an activity is
recognized, the 21440 starts to process the incoming data.
In the MII mode, the 21440 detects activity when the data valid signal (dv{i}) asserts.
After detecting receive activity on the line, the 21440 starts to process the preamble bytes.
Destination
Address
Source Address
Type
Op-Code
Pause
Time
Padding
FCS
Byte
Count
6
6
2
2
2
42
4
Value
(Canonic
Form)
01-80-C2-00-00-01
EA1-EA2-..-EA6
88 - 08
00 - 01
PT1 - PT2
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PDF描述
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