參數(shù)資料
型號(hào): 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁(yè)數(shù): 15/92頁(yè)
文件大?。?/td> 1352K
代理商: 21440
21440 Multiport 10/100Mb/s Ethernet Controller
2-3
Pinout
rxctl_l
I
Receive control enable.
When asserted, this pin enables rxrdy{i} output drivers to report receive FIFO status.
Transmit FIFO ready.
Indicates whether there is enough available space in the transmit FIFO to load data
according to the programmable threshold value. Following transmission stop due to an
error, the txrdy signal remains deasserted until the transmit error status is read.
Receive FIFO ready.
Indicates whether there is enough available data in the receive FIFO to be stored
according to the programmable threshold value or if the end of the transferred packet is
in the FIFO. The rxrdy signal may also be asserted when the packet header is in the
FIFO. rxrdy can also be asserted to report packet discard from the receive FIFO due to
an error together with the rxfail signal.
Vdd clamp.
Should be connected to the power of the highest signal level used on the FIFO bus.
txrdy{i}
O
rxrdy{i}
O
Vdd_clmp
I
MII / SYM Interface
Note:
The pins have various functions according to the port mode: MII or SYM. See a detailed
description in
Section 6
, Network Interface Operation.
Transmit clock.
MII mode:
Nibble transmit data.
SYM mode:
Four low bits of the encoded transmit data.
MII mode:
Transmit enable signal.
SYM mode:
The fifth bit of the encoded transmit data.
Receive recovered clock.
MII mode:
Nibble receive data.
SYM mode:
Four low bits of the encoded received data.
MII mode:
Receive enable signal.
SYM mode:
The fifth bit of the encoded received data.
I/O
MII mode:
Collision detection signal (input).
SYM mode:
Activity indication (output).
I
MII mode:
Carrier detection signal.
SYM mode:
Signal detection indicating link status.
I
MII mode:
Receive error signal.
SYM mode:
Must be connected to 0.
O
MII mode:
Transmit error signal.
SYM mode:
Link indication.
O
MII management clock.
I/O
MII management input/output serial data.
JTAG Interface
tck
I
JTAG clock. If this pin is not used, it must be connected to 0.
tms
I
JTAG test mode. If this pin is not used, it must be connected to 1.
tdi
I
JTAG data serial input. If this pin is not used, it must be connected to 1.
tdo
O
JTAG data serial output.
tclk{i}
txd{i}[3:0]
I
O
ten{i}/txd{i}[4]
O
rclk{i}
rxd{i}[3:0]
I
I
dv{i}/rxd{i}[4]
I
col{i}/act{i}
crs{i}/sd{i}
rerr{i}
terr{i}/lnk{i}
mdc
mdio
Table 2-1. Signal Descriptions (Sheet 3 of 3)
Signal Name
I/O
Pin Description
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