參數(shù)資料
型號: 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 14/92頁
文件大小: 1352K
代理商: 21440
Pinout
2-2
21440 Multiport 10/100Mb/s Ethernet Controller
FIFO Interface
clk
I
System clock.
All the FIFO data transfers are synchronized to this clock.
Transmit select.
This pin must be asserted to enable transmit FIFO write access.
Receive select.
This pin must be asserted to enable receive FIFO read access.
The following signals are driven upon assertion of rxsel_l: fdat[63:0], fbe_l[7:0], sop, eop
and rxfail.
FIFO port select.
Selects one of the port FIFOs for data transfer.
FIFO data bus.
Carries the data to be written to the transmit FIFO or read from the receive FIFO of the
selected port. When operating in 32-bit mode, the unused pins (fdat[63:32]) should be
connected to pull-up resistors.
FIFO byte enable.
During transmit, indicates which of the bytes driven onto fdat[63:0] contain valid data (valid
bytes need to be contiguous and at least one byte must be valid). During receive, indicates
which bytes are valid. Each fbe_l signal relates to a different fdat byte (for example, fbe_l[0]
relates to fdat[7:0] and fbe_l[5] relates to fdat[47:40]). When operating in 32-bit mode, the
unused pins (fbe_l[7:4]) should be connected to pull-up resistors.
Receive keep.
When asserted, this signal causes the last read data to be kept in the receive FIFO. May
be asserted only with rxsel_l assertion.
Start of packet.
When asserted during transmit, indicates that the first data in the packet is written to the
transmit FIFO. During receive, this signal is asserted when the first data of the packet is
read from the receive FIFO.
End of packet.
When asserted during transmit, indicates that the final data in the packet is written to the
transmit FIFO. During receive, eop is asserted when the final data of the packet is read
from the receive FIFO. In the following FIFO access, the packet status is driven onto the
bus.
Transmit as is/Transmit error.
When asserted during transmit, upon transfer of the packet
s first data (together with sop
assertion), no padding and/or CRC is appended to the packet even if the port was
programmed to do so. When asserted upon transfer of the packet
s final data (together
with eop assertion), the packet is transmitted with an MII error (if the port is programmed
to append CRC) and with a symbol error.
Receive packet failure.
This signal is asserted if a packet was received with errors, had started to appear on the
FIFO bus, and was discarded from the receive FIFO.
Receive abort.
This signal forces a received packet to be aborted and flushed from the receive FIFO.
May be asserted only with rxsel_l assertion.
Flow control.
When asserted in the half-duplex mode, a collision is generated on each received
packet. When asserted in the full-duplex mode, a flow-control packet with the
programmed pause time is transmitted. Upon deassertion, a flow-control packet with
time equal to 0 is sent if programmed accordingly.
Transmit control enable.
When asserted, this pin enables txrdy{i} output drivers to report the transmit FIFO status.
txsel_l
I
rxsel_l
I
fps[2:0]
I
fdat[63:0]
I/O
fbe_l[7:0]
I/O
rxkep
I
sop
I/O
eop
I/O
txasis/txerr
I
rxfail
O
rxabt
I
flct{i}
I
txctl_l
I
Table 2-1. Signal Descriptions (Sheet 2 of 3)
Signal Name
I/O
Pin Description
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