參數(shù)資料
型號: 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 80/92頁
文件大小: 1352K
代理商: 21440
Electrical and Environmental Specifications
8-4
21440 Multiport 10/100Mb/s Ethernet Controller
8.6.3
5 Volt DC Specifications
Table 8-9
lists the DC parameters for the FIFO bus 5 V signaling levels.
8.6.4
FIFO Bus Signals Timing
Figure 8-2
shows the FIFO bus signals timing diagram.
Table 8-10
lists the timing specifications of the FIFO bus signals.
Table 8-9. FIFO Bus 5-V Signaling Specifications
Symbol
Parameter
Condition
Minimum
Maximum
Vih
Input high voltage
2.0 V
0.5 V
2
Vdd_clmp + 0.5 V
1
1.
2.
Overvoltage protection maximum is +11 V through a series 29
resistor for 11 ns.
Overvoltage protection minimum is
5.5 V through a series 28
resistor for 11 ns.
Vil
Input low voltage
0.8 V
Ii
Input leakage current
0.5 V < Vin < 2.7 V
15 μA
15 μA
Voh
Output high voltage
Iout =
2 mA
2.4 V
Vol
Output low voltage
Iout = 6 mA
0.55 V
Cin
Pin capacitance
5 pF
10 pF
Figure 8-2. FIFO Bus Signals Timing Diagram
Table 8-10. FIFO Bus Signals Timing Specifications
Symbol
Parameter
Minimum (ns)
Maximum (ns)
Tval
Clock-to-signal valid delay
2
7
Tsu
Input signal valid setup time before clock
4
Th
Input signal hold time from clock
0
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