參數(shù)資料
型號(hào): 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁(yè)數(shù): 32/92頁(yè)
文件大?。?/td> 1352K
代理商: 21440
Register Descriptions
3-12
21440 Multiport 10/100Mb/s Ethernet Controller
3.2.3.2
FIFO Bus Mode Register
The FIFO bus mode register controls the FIFO bus mode of work.
Bit Name
Bit Number
Bit Description
7:3
RESERVED
HRYD
2
Header ready disable.
When set, the rxrdy signal will not be asserted when a packet header is in
FIFO, but only according to FIFO threshold values.
BWID
1
Bus width.
Defines the number of bits used on the FIFO bus. When set, 64 bits are used.
When reset, the lower 32 bits are used.
BEND
0
Big or little endian mode.
Defines the byte ordering mode on the FIFO bus. When set, the port uses the
big endian mode. When reset, the little endian mode is used.
Access Rules
Register access
R/W
Value after reset
00H
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