參數(shù)資料
型號(hào)： 21440
廠商： Intel Corp.
英文描述： Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述： 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器）
文件頁數(shù)： 52/92頁
文件大?。?/td> 1352K
代理商： 21440
21440 Multiport 10/100Mb/s Ethernet Controller
4-7
FIFO Interface Operation
4.3.4
Packet Abortion
During the transfer of a received packet onto the FIFO bus, the 21440 supports the ability to
prevent any further transfer of this packet. At any time during packet reception, the packet may be
dynamically discarded from the receive FIFO by asserting the rxabt signal during packet reading.
Any subsequent packet loaded into the receive FIFO is not affected by rxabt assertion. The next
FIFO access will be the next packet.
4.3.5
Network Reception
A packet received from the network is loaded into the receive FIFO. If the packet is received
without any error, it is transferred to the FIFO bus. If an error occurs during reception, the packet is
handled according onto the programming.
The 21440 may be programmed to work in two modes: reject the erroneous packet or accept it
(RX_FILT_MOD). In both modes, according to the error, the appropriate statistic counters will be
updated, even if the packet was rejected due to packet error or FIFO overflow. Even in case of
errors, any following packets continue to be accepted and loaded to the receive FIFO.
The following events are considered as reception errors:
FIFO overflow
CRC error
Alignment error
Short packet
Too long packet
MII error
4.3.6
Rejecting Mode on Reception Errors
If a packet with a reception error is programmed to be rejected, the 21440 discards the packet from
the receive FIFO without affecting previous packets that may still be in the receive FIFO. If the
packet had not yet started to be transferred on the FIFO bus, it will be discarded without affecting
FIFO bus activity. If the packet had already started to be transferred onto the FIFO bus, or rxrdy
was already asserted, the rxfail signal will be asserted on the next FIFO access, indicating that the
currently transferred packet was discarded from the receive FIFO. Packet status will not be driven
for such a packet.
Runt packets that may be received due to collision on the network can be filtered by the 21440 by
programming the receive threshold to be greater than 64 bytes.
4.3.7
Accepting Mode on Reception Errors
If a packet with a specific event is programmed to be accepted, it is transferred to the FIFO bus as a
regular packet and the event type is reported in the packet status appended to the end of the packet.
Such a packet may also generate an interrupt, if programmed to do so. The cause of the interrupt is
reported in the receive status register (RECV_STT).
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