參數(shù)資料
型號: 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 79/92頁
文件大?。?/td> 1352K
代理商: 21440
21440 Multiport 10/100Mb/s Ethernet Controller
8-3
Electrical and Environmental Specifications
8.6
FIFO Port Specifications
This section describes the FIFO port specifications.
8.6.1
Clock Specification
Figure 8-1
shows the FIFO bus clock timing diagram.
Table 8-7
lists the specifications of the FIFO bus clock.
8.6.2
3.3 Volt DC Specifications
Table 8-8
lists the DC parameters for the FIFO bus 3.3 V signaling levels.
Figure 8-1. FIFO Bus Clock Timing Diagram
Table 8-7. FIFO Bus Clock Timing Specifications
Symbol
Parameter
Condition
Minimum
Maximum
Freq
Tc
Th
Tl
Clock frequency
Cycle time
Clock high time
Clock low time
Clock peak to peak
(0.2
×
Vdd to 0.6
×
Vdd)
Clock high threshold
Clock low threshold
Clock peak to peak (0.4 V to 2.4 V)
Clock high threshold
Clock low threshold
25 MHz
1
15 ns
6 ns
6 ns
1.
For testing purposes, the minimum frequency is 16 MHz.
66.6 MHz
40 ns
Vptp
3.3 V clock
0.4
×
Vdd
Vh
Vl
Vptp
Vh
Vl
3.3 V clock
3.3 V clock
5 V clock
5 V clock
5 V clock
0.5
×
Vdd
2 V
2 V
0.3
×
Vdd
0.8 V
Table 8-8. FIFO Bus 3.3 V Signaling Specifications
Symbol
Parameter
Condition
Minimum
Maximum
Vdd_clmp + 0.5 V
1
0.3
×
Vdd
15 μA
0.1
×
Vdd
10 pF
Vih
Vil
Ii
Voh
Vol
Cin
Input high voltage
Input low voltage
Input leakage current
Output high voltage
Output low voltage
Pin capacitance
0 < Vin < Vdd
Iout =
500 μA
Iout = 1500 μA
0.5
×
Vdd
0.5 V
2
15 μA
0.9
×
Vdd
5 pF
1.
2.
Overvoltage protection maximum is +7.1 V through a series 29
resistor for 11 ns.
Overvoltage protection minimum is
3.5 V through a series 28
resistor for 11 ns.
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