參數(shù)資料
型號(hào)： 21440
廠商： Intel Corp.
英文描述： Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述： 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器）
文件頁(yè)數(shù)： 4/92頁(yè)
文件大?。?/td> 1352K
代理商： 21440
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21440 Multiport 10/100Mb/s Ethernet Controller
3.3.2
Access Sequences.....................................................................................3-24
3.4.1
Initialization Sequence...................................................................3-24
3.4.2
Mode Change Sequence...............................................................3-24
3.4.3
Interrupt Handling Sequence.........................................................3-25
Network Statistic Counters Access Rules......................................3-24
3.4
4
FIFO Interface Operation...........................................................................................4-1
4.1
FIFO Interface...............................................................................................4-1
4.1.1
Byte Ordering on FIFO Bus ............................................................4-1
4.1.2
FIFO Status Signaling......................................................................4-2
4.2
Packet Transmission ....................................................................................4-2
4.2.1
Packet Loading................................................................................4-2
4.2.2
Network Transmission .....................................................................4-3
4.2.3
Excessive Collisions ........................................................................4-3
4.2.4
Late Collision ...................................................................................4-3
4.2.5
FIFO Underflow ...............................................................................4-3
4.2.6
Stopping Mode on Transmission Errors...........................................4-4
4.2.7
Transmit Flow Diagram....................................................................4-4
4.3
Packet Reception..........................................................................................4-5
4.3.1
Packet Storing .................................................................................4-5
4.3.2
Header Preprocessing.....................................................................4-6
4.3.3
Packet Segmentation.......................................................................4-6
4.3.4
Packet Abortion ...............................................................................4-7
4.3.5
Network Reception ..........................................................................4-7
4.3.6
Rejecting Mode on Reception Errors...............................................4-7
4.3.7
Accepting Mode on Reception Errors..............................................4-7
4.3.8
Receive Flow Diagram.....................................................................4-8
5
CPU Interface Operation ...........................................................................................5-1
5.1
CPU Interface ...............................................................................................5-1
5.2
Network Management...................................................................................5-1
5.2.1
SNMP MIB Support .........................................................................5-2
5.2.2
RMON Statistic Group Support........................................................5-3
5.2.3
RMON Host Group Support.............................................................5-4
6
Network Interface Operation......................................................................................6-1
6.1
Operating Modes..........................................................................................6-1
6.2
MII Port Interface ..........................................................................................6-2
6.3
MAC Frame Format......................................................................................6-3
6.4
MAC Transmit Operation..............................................................................6-4
6.4.1
Transmit Initiation ............................................................................6-4
6.4.2
Initial Deferral...................................................................................6-4
6.4.3
Frame Encapsulation.......................................................................6-4
6.4.4
Collision ...........................................................................................6-5
6.4.5
Terminating Transmission................................................................6-5
6.4.6
Backpressure...................................................................................6-6
6.4.7
Flow Control.....................................................................................6-6
6.5
MAC Receive Operation...............................................................................6-6
6.5.1
Receive Initiation .............................................................................6-6
6.5.2
Preamble Processing.......................................................................6-7
6.5.3
Frame Decapsulation.......................................................................6-7
6.5.4
Terminating Reception.....................................................................6-7
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