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January 1994
COPYRIGHT
INTEL CORPORATION, 1995
Order Number: 240187-008
Intel386
TM
SX MICROPROCESSOR
Y
Full 32-Bit Internal Architecture
D 8-, 16-, 32-Bit Data Types
D 8 General Purpose 32-Bit Registers
Y
Runs Intel386
TM
Software in a Cost
Effective 16-Bit Hardware Environment
D Runs Same Applications and O.S.’s
as the Intel386
TM
DX Processor
D Object Code Compatible with 8086,
80186, 80286, and Intel386
TM
Processors
Y
High Performance 16-Bit Data Bus
D 16, 20, 25 and 33 MHz Clock
D Two-Clock Bus Cycles
D Address Pipelining Allows Use of
Slower/Cheaper Memories
Y
Integrated Memory Management Unit
D Virtual Memory Support
D Optional On-Chip Paging
D 4 Levels of Hardware Enforced
Protection
D MMU Fully Compatible with Those of
the 80286 and Intel386 DX CPUs
Y
Virtual 8086 Mode Allows Execution of
8086 Software in a Protected and
Paged System
Y
Large Uniform Address Space
D 16 Megabyte Physical
D 64 Terabyte Virtual
D 4 Gigabyte Maximum Segment Size
Y
Numerics Support with the Intel387
TM
SX Math CoProcessor
Y
On-Chip Debugging Support Including
Breakpoint Registers
Y
Complete System Development
Support
D Software: C, PL/M, Assembler
D Debuggers: PMON-386 DX,
ICE
TM
-386 SX
Y
High Speed CHMOS IV Technology
Y
Operating Frequency:
D Standard
(Intel386 SX -33, -25, -20, -16)
Min/Max Frequency
(4/33, 4/25, 4/20, 4/16) MHz
D Low Power
(Intel386 SX -33, -25, -20, -16, -12)
Min/Max Frequency
(2/33, 2/25, 2/20, 2/16, 2/12) MHz
Y
100-Pin Plastic Quad Flatpack Package
(See Packaging Outlines and Dimensions
Y
231369)
The Intel386
TM
SX Microprocessor is an entry-level 32-bit CPU with a 16-bit external data bus and a 24-bit
external address bus. The Intel386 SX CPU brings the vast software library of the Intel386
TM
Architecture to
entry-level systems. It provides the performance benefits of a 32-bit programming architecture with the cost
savings associated with 16-bit hardware systems.
240187–47
Intel386
TM
SX Pipelined 32-Bit Microarchitecture